ATMEGA163L-4AC Atmel, ATMEGA163L-4AC Datasheet - Page 51

• Manufacturer Part Number: ATMEGA163L-4AC
• Description: IC AVR MCU 16K A/D 2.7V 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA163L-4AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8-bit Timer/Counter 2
1142E–AVR–02/03
In overflow PWM mode, the table above is only valid for OCR1X = TOP.
In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from
$00 00. In overflow PWM mode, the Timer Overflow Flag is set as in Normal
Timer/Counter mode. Timer Overflow Interrupt1 operates exactly as in Normal
Timer/Counter mode, i.e., it is executed when TOV1 is set provided that Timer Overflow
Interrupt1 and global interrupts are enabled. This also applies to the Timer Output
Compare1 Flags and interrupts.
Figure 37 shows the block diagram for Timer/Counter2.
Figure 37. Timer/Counter2 Block Diagram
The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external
crystal input TOSC1. It can also be stopped as described in the section “Timer/Counter2
Control Register – TCCR2” on page 52.
The Status Flags (Overflow and Compare Match) are found in the Timer/Counter Inter-
rupt Flag Register – TIFR. Control signals are found in the Timer/Counter Control
Register TCCR2. The interrupt enable/disable settings are found in “The Timer/Counter
Interrupt Mask Register – TIMSK” on page 31.
When Timer/Counter2 is externally clocked, the external signal is synchronized with the
Oscillator frequency of the CPU. To assure proper sampling of the external clock, the
minimum time between two external clock transitions must be at least one internal CPU
7
7
7
8-BIT COMPARATOR
TIMER/COUNTER2
OUTPUT COMPARE
REGISTER2 (OCR2)
REGISTER (TIMSK)
TIMER INT. MASK
8-BIT DATA BUS
8-BIT ASYNCH T/C2 DATA BUS
(TCNT2)
PCK2
0
0
0
CK
T/C2 OVER-
FLOW IRQ
T/C CLEAR
T/C CLK SOURCE
UP/DOWN
REGISTER (TIFR)
TIMER INT. FLAG
SYNCH UNIT
T/C2 COMPARE
MATCH IRQ
CONTROL
LOGIC
ATmega163(L)
REGISTER (TCCR2)
REGISTER (ASSR)
ASYNCH. STATUS
T/C2 CONTROL
CK
PSR2
TOSC1
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