ATMEGA163L-4AC Atmel, ATMEGA163L-4AC Datasheet - Page 71

• Manufacturer Part Number: ATMEGA163L-4AC
• Description: IC AVR MCU 16K A/D 2.7V 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA163L-4AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ATmega163(L)
When data is transferred from UDR to the Shift Register, the UDRE (UART Data Regis-
ter Empty) bit in the UART Status Register, USR, is set. When this bit is set (one), the
UART is ready to receive the next character. At the same time as the data is transferred
from UDR to the 10(11)-bit Shift Register, bit 0 of the Shift Register is cleared (start bit)
and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9 bit in the UART
Control Register, UCR is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit
Shift Register.
On the Baud Rate clock following the transfer operation to the Shift Register, the start bit
is shifted out on the TXD pin. Then follows the data, LSB first. When the stop bit has
been shifted out, the Shift Register is loaded if any new data has been written to the
UDR during the transmission. During loading, UDRE is set. If there is no new data in the
UDR Register to send when the stop bit is shifted out, the UDRE Flag will remain set
until UDR is written again. When no new data has been written, and the stop bit has
been present on TXD for one bit length, the Transmit Complete Flag, TXC, in USR is
set.
The TXEN bit in UCR enables the UART transmitter when set (one). When this bit is
cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART
Transmitter will be connected to PD1, which is forced to be an output pin regardless of
the setting of the DDD1 bit in DDRD.
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