ATMEGA645-16AI Atmel, ATMEGA645-16AI Datasheet - Page 56

• Manufacturer Part Number: ATMEGA645-16AI
• Description: IC AVR MCU FLASH 64K 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA645-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

12.2
12.2.1
2570M–AVR–04/11
Register Description
EICRA – External Interrupt Control Register A
Figure 12-1. Pin Change Interrupt
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 12-1.
Bit
(0x69)
Read/Write
Initial Value
ISC01
0
0
1
1
pcint_setflag
pcint_in_(n)
PCINT(n)
pcint_syn
pin_sync
ISC00
pin_lat
Interrupt 0 Sense Control
PCINT(0)
PCIF
R
7
–
0
0
1
0
1
clk
clk
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
LE
R
6
–
0
Table
pin_lat
D
12-1. The value on the INT0 pin is sampled before detecting
R
5
–
0
Q
pin_sync
PCINT(0) in PCMSK(x)
4
–
R
0
ATmega325/3250/645/6450
pcint_in_(0)
R
3
–
0
0
x
clk
R
2
–
0
pcint_syn
ISC01
R/W
1
0
pcint_setflag
ISC00
R/W
0
0
EICRA
PCIF
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