EP9301-CQ Cirrus Logic Inc, EP9301-CQ Datasheet - Page 2

• Manufacturer Part Number: EP9301-CQ
• Description: IC ARM920T MCU 166MHZ 208-LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQ

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 598-1248

Ethernet
HDLC
2
Description 1
The Ethernet controller does not correctly receive frames that have a size of 64 bytes.
Workaround
In order to receive frames of 64 bytes, enable the RCRCA bit in RxCTL. This will prevent the Ethernet
controller from discarding the 64-byte-long frames.
Description 2
When there is inadequate AHB bus bandwidth for data to be transferred from the Ethernet controller FIFO
to the receive descriptor, the Ethernet FIFO will overflow and cause the Ethernet controller to fail to receive
any more packets.
This problem will also occur if the processor is too busy to service incoming packets in a timely manner. By
the time that new receive descriptors are available, the data in the FIFO will contain frames that are
corrupted.
It is the job of the system designer to ensure that there is adequate bandwidth for the applications being run.
Workaround
This is a rare occurrence, however at a system level it is important to reserve adequate bandwidth for the
Ethernet controller. This can be accomplished by some of the following:
Description
When the final byte of a received packet is read into the DMA controller's buffer, the software will be notified
by an HDLC RFC interrupt. However, the DMA controller may not have written the currently buffered part of
the packet to memory, so that the last one to fifteen bytes of a packet may not be accessible.
Workaround
To insure that the DMA channel empties the buffer, do the following (in the HDLC interrupt handler, for
example):
1) Note the values in the MAXCNTx and REMAIN registers for the DMA channel. The difference is the num-
ensure that the controller never runs out of receive descriptors.
ber of bytes read from the UART/HDLC, which is the size of the HDLC packet. Call this number N. Note
that the BC field of the UART1HDLCRXInfoBuf register should also be N.
- Reducing the bandwidth use of other bus masters in the system.
- Lowering Ethernet rate to half duplex or 10Mbit if higher bandwidth is not required.
- Insuring that the Ethernet controller receive descriptor processing is given a high enough priority to
ER636E2B