MC68HC908GT16CFB Freescale Semiconductor, MC68HC908GT16CFB Datasheet - Page 171

• Manufacturer Part Number: MC68HC908GT16CFB
• Description: IC MCU 16K FLASH 8MHZ SPI 44PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GT16CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 36
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.8.6 ESCI Data Register
The ESCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the ESCI data register.
R7/T7:R0/T0 — Receive/Transmit Data Bits
14.8.7 ESCI Baud Rate Register
The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for
both the receiver and the transmitter.
LINR — LIN Receiver Bits
Freescale Semiconductor
Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018
writes the data to be transmitted, T7:T0. Reset has no effect on the ESCI data register.
This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol
as shown in
Address:
Address:
There are two prescalers available to adjust the baud rate. One in the ESCI
baud rate register and one in the ESCI prescaler register.
Table
Reset:
Reset:
Read:
Read:
Write:
Write:
LINR
Do not use read-modify-write instructions on the ESCI data register.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
0
1
1
14-6. Reset clears LINR.
$0018
$0019
Bit 7
Bit 7
R7
T7
R
0
Figure 14-17. ESCI Baud Rate Register (SCBR)
M
X
0
1
Figure 14-16. ESCI Data Register (SCDR)
= Unimplemented
Normal ESCI functionality
11-bit break detect enabled for LIN receiver
12-bit break detect enabled for LIN receiver
LINR
R6
T6
6
6
0
Table 14-6. ESCI LIN Control Bits
SCP1
R5
T5
5
5
0
NOTE
NOTE
Unaffected by reset
SCP0
R4
T4
R
4
4
0
Functionality
= Reserved
R3
T3
R
3
3
0
SCR2
R2
T2
2
2
0
SCR1
R1
T1
1
1
0
SCR0
Bit 0
Bit 0
R0
T0
0
I/O Registers
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