L4925PD STMicroelectronics, L4925PD Datasheet - Page 9

IC REG LDO 5V 20POWERSOIC

L4925PD

Manufacturer Part Number
L4925PD
Description
IC REG LDO 5V 20POWERSOIC
Manufacturer
STMicroelectronics
Datasheet

Specifications of L4925PD

Regulator Topology
Positive Fixed
Voltage - Output
5V
Voltage - Input
6 ~ 28 V
Voltage - Dropout (typical)
0.3V @ 500mA
Number Of Regulators
1
Current - Output
500mA
Current - Limit (min)
550mA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
PowerSO-20 Exposed Bottom Pad
Number Of Outputs
1
Polarity
Positive
Input Voltage Max
28 V
Output Voltage
5 V
Output Type
Fixed
Dropout Voltage (max)
0.6 V
Output Current
500 mA
Line Regulation
10 mV
Load Regulation
50 mV
Voltage Regulation Accuracy
1 %
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Reference Voltage
1.23 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-3912-5

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L4925
3.2
Figure 4.
Figure 5.
Reset circuit
The block circuit diagram of the reset circuit is shown in
supervises the output voltage. The reset threshold of 4.5 V is defined with the internal
reference voltage and standby output divider. The reset pulse delay time t
the charge time of an external capacitor CT:
The reaction time of the reset circuit originates from the discharge time limitation of the reset
capacitor CT and it is proportional to the value of CT. The reaction time of the reset circuit
increases the noise immunity. Standby output voltage drops below the reset threshold only a
bit longer than the reaction time results in a shorter reset delay time.
The nominal reset delay time is generated for standby output voltage drops longer than
approximately 50 ms. The typical reset output waveforms are shown in
t
RD
=
C
-------------------
2μA
T
2V
Output voltage vs input voltage
Quiescent current vs supply voltage
Doc ID 1770 Rev 7
Figure
6. The reset circuit
Functional description
Figure
RD
, is defined with
7.
9/14

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