ST16C552CJ68-F Exar Corporation, ST16C552CJ68-F Datasheet - Page 16

• Manufacturer Part Number: ST16C552CJ68-F
• Description: IC UART FIFO PAR 16B DUAL 68PLCC
• Manufacturer: Exar Corporation
• Type: Dual UART with 16-byte FIFOs and Parallel Printer Portr

Specifications of ST16C552CJ68-F

• Number Of Channels: 2, DUART
• Package / Case: 68-LCC (J-Lead)
• Features: *
• Fifo's: 16 Byte
• Protocol: Printer
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Parallel Port: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 2
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1263-5

ST16C552/552A
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the eighteen 552/552A internal registers. The
assigned bit functions are more fully defined in the following paragraphs.
Rev. 3.40
A2 A1 A0
0
0
0
0
0
0
1
1
1
1
0
0
Table 7, ST16C552/552A INTERNAL REGISTERS
General Register Set: Note 1*
Special Register Set: Note *2
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
RHR [XX]
MSR [X0]
THR [XX]
MCR [00]
SPR [FF]
DLM [XX]
Register
[Default]
FCR [00]
LCR [00]
DLL [XX]
LSR [60]
IER [00]
ISR [01]
Note 5*
enabled
FIFO’s
RCVR
trigger
(MSB)
divisor
enable
BIT-7
bit-15
down
FIFO
latch
error
bit-7
bit-7
data
bit-7
bit-7
Pwr
CD
0
enabled
FIFO’s
THR &
RCVR
trigger
empty
BIT-6
(LSB)
bit-14
break
TSR
bit-6
bit-6
bit-6
bit-6
set
RI
0
0
empty
BIT-5
mode
bit-13
down
parity
THR.
DSR
bit-5
bit-5
bit-5
bit-5
Pwr
En
set
0
0
0
16
interrupt
BIT-4
break
bit-12
parity
even
back
CTS
bit-4
bit-4
loop
bit-4
bit-4
0
0
0
Interrupt
INT A/B
framing
Modem
priority
enable
enable
Status
select
BIT-3
mode
bit-11
DMA
parity
delta
bit-3
bit-3
bit-2
error
bit-3
bit-3
-CD
INT
interrupt
Receive
Status
priority
BIT-2
XMIT
bit-10
FIFO
parity
reset
delta
bit-2
bit-2
bit-1
error
bit-2
bit-2
Line
stop
INT
bits
-RI
[X]
Transmit
Register
interrupt
Holding
overrun
RCVR
priority
length
BIT-1
-RTS
-DSR
FIFO
reset
word
error
delta
bit-1
bit-1
bit-0
bit-1
bit-1
bit-1
bit-9
INT
Register
Receive
Holding
receive
enable
status
length
BIT-0
-DTR
ready
-CTS
FIFO
word
delta
bit-0
bit-0
bit-0
bit-0
bit-0
bit-8
data
INT