EM35X-BBRD Ember, EM35X-BBRD Datasheet - Page 157
EM35X-BBRD
Manufacturer Part Number
EM35X-BBRD
Description
EM35X BREAKOUT BOARD
Manufacturer
Ember
Datasheet
1.EM35X-DEV-UPG-IAR.pdf
(245 pages)
Specifications of EM35X-BBRD
Frequency
2.4GHz
For Use With/related Products
EM35x
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
636-1013
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TIMx_CR2
TIM1_CR2
Timer 1 Control Register 2
TIM2_CR2
Timer 2 Control Register 2
Bitname
TIM_TI1S
TIM_MMS
TIM_TI1S
31
23
15
7
0
0
0
30
22
14
0
0
0
6
Bitfield
[6:4]
[7]
TIM_MMS
29
21
13
0
0
0
5
Access
RW
RW
Description
TI1 Selection.
0: TI1M (input of the digital filter) is connected to TI1 input.
1: TI1M is connected to the TI_HALL inputs (XOR combination).
Master Mode Selection.
This selects the information to be sent in master mode to a slave timer for
synchronization using the trigger output (TRGO).
000: Reset - the TIM_UG bit in the TMRx_EGR register is trigger output.
If the reset is generated by the trigger input (slave mode controller configured in reset
mode), then the signal on TRGO is delayed compared to the actual reset.
001: Enable - counter enable signal CNT_EN is trigger output.
This mode is used to start both timers at the same time or to control a window in which a
slave timer is enabled. The counter enable signal is generated by either the TIM_CEN
control bit or the trigger input when configured in gated mode. When the counter enable
signal is controlled by the trigger input there is a delay on TRGO except if the
master/slave mode is selected (see the TIM_MSM bit description in TMRx_SMCR register).
010: Update - UEV is trigger output.
This mode allows a master timer to be a prescaler for a slave timer.
011: Compare Pulse.
The trigger output sends a positive pulse when the TIM_CC1IF flag is to be set (even if it
was already high) as soon as a capture or a compare match occurs.
100: Compare - OC1REF signal is trigger output.
101: Compare - OC2REF signal is trigger output.
110: Compare - OC3REF signal is trigger output.
111: Compare - OC4REF signal is trigger output.
28
20
12
4
0
0
0
Final
9-33
27
19
11
0
0
0
3
0
26
18
10
2
0
0
0
0
Address: 0x4000F004 Reset: 0x0
Address: 0x4000E004 Reset: 0x0
25
17
0
0
9
0
1
0
120-035X-000G
24
16
0
0
8
0
0
0
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