EM35X-BBRD Ember, EM35X-BBRD Datasheet - Page 164
![EM35X BREAKOUT BOARD](/photos/14/8/140871/em35x-bbrd_sml.jpg)
EM35X-BBRD
Manufacturer Part Number
EM35X-BBRD
Description
EM35X BREAKOUT BOARD
Manufacturer
Ember
Datasheet
1.EM35X-DEV-UPG-IAR.pdf
(245 pages)
Specifications of EM35X-BBRD
Frequency
2.4GHz
For Use With/related Products
EM35x
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
636-1013
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TIMx_CCMR2
TIM1_CCMR2
Timer 1 Capture/Compare Mode Register 2
TIM2_CCMR2
Timer 2 Capture/Compare Mode Register 2
Timer channels can be programmed as inputs (capture mode) or outputs (compare mode). The direction of channel y is defined by TIM_CCyS in this
register.
The other bits in this register have different functions in input and in output modes. The TIM_OC* fields only apply to a channel configured as an
output (TIM_CCyS = 0), and the TIM_IC* fields only apply to a channel configured as an input (TIM_CCyS > 0).
Bitname
TIM_OC4M
TIM_OC4BE
31
23
15
0
0
0
7
0
30
22
14
6
0
0
Bitfield
[14:12]
TIM_IC4F
TIM_IC3F
[11]
TIM_OC4M
TIM_OC3M
29
21
13
0
0
5
Access
RW
RW
Description
Output Compare 4 Mode. (Applies only if TIM_CC4S = 0.)
Define the behavior of the output reference signal OC4REF from which OC4 derives.
OC4REF is active high whereas OC4’s active level depends on the TIM_CC4P bit.
000: Frozen - The comparison between the output compare register TIMx_CCR4 and the
counter TIMx_CNT has no effect on the outputs.
001: Set OC4REF to active on match. The OC4REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 4 (TIMx_CCR4)
010: Set OC4REF to inactive on match. OC4REF signal is forced low when the counter
TIMx_CNT matches the capture/compare register 4 (TIMx_CCR4).
011: Toggle - OC4REF toggles when TIMx_CNT = TIMx_CCR4.
100: Force OC4REF inactive.
101: Force OC4REF active.
110: PWM mode 1 - In up-counting, OC4REF is active as long as TIMx_CNT < TIMx_CCR4,
otherwise OC4REF is inactive. In down-counting, OC4REF is inactive if
TIMx_CNT > TIMx_CCR4, otherwise OC4REF is active.
111: PWM mode 2 - In up-counting, OC4REF is inactive if TIMx_CNT < TIMx_CCR4,
otherwise OC4REF is active. In down-counting, OC4REF is active if TIMx_CNT > TIMx_CCR4,
otherwise it is inactive.
Note: In PWM mode 1 or 2, the OC4REF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode to
“PWM” mode.
Output Compare 4 Buffer Enable. (Applies only if TIM_CC4S = 0.)
0: Buffer register for TIMx_CCR4 is disabled. TIMx_CCR4 can be written at anytime, the
new value is used by the shadow register immediately.
1: Buffer register for TIMx_CCR4 is enabled. Read/write operations access the buffer
register. TIMx_CCR4 buffer value is loaded in the shadow register at each UEV.
Note: The PWM mode can be used without enabling the buffer register only in one pulse
mode (TIM_OPM bit set in the TIMx_CR2 register), otherwise the behavior is undefined.
28
20
12
0
0
4
Final
9-40
TIM_OC4BE
TIM_OC3BE
27
19
11
3
0
0
TIM_IC4PSC
TIM_IC3PSC
TIM_OC4FE
TIM_OC3FE
26
18
10
0
0
2
Address: 0x4000E01C Reset: 0x0
Address: 0x4000F01C Reset: 0x0
25
17
0
0
9
1
TIM_CC4S
TIM_CC3S
120-035X-000G
24
16
8
0
0
0
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