ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 34
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 34 of 555
- Download datasheet (6Mb)
Table 9-1. SLPTR Multi-functional Configuration bit
9.3.2 Interrupt Logic
9.3.2.1 Overview
34
Transceiver Status
PLL_ON
TX_ARET_ON
TRX_OFF
SLEEP
ATmega128RFA1
Function
TX start
TX start
Sleep
Wakeup
The register (TRXRST) can be used to reset the transceiver without resetting the
controller. After the reset bit was set, it is cleared immediately.
A second configuration bit (SLPTR) is used to control frame transmission or sleep and
wakeup of the transceiver. This bit is not cleared automatically.
The function of the SLPTR bit relates to the current state of the transceiver module and
is summarized in
section
In states PLL_ON and TX_ARET_ON, bit SLPTR is used to initiate a TX transaction.
Here bit SLPTR is sensitive on the transition from “0” to “1” only. The bit should be
cleared before the frame transmission is finished.
After initiating a state change by a “0” to “1” transition at bit SLPTR in radio transceiver
states TRX_OFF, RX_ON or RX_AACK_ON, the radio transceiver remains in the new
state as long as the bit is logical “1” and returns to the preceding state if the bit is set to
“0”.
SLEEP state
The SLEEP state is used when radio transceiver functionality is not required, and thus
the receiver module can be powered down to reduce the overall power consumption.
When the radio transceiver is in TRX_OFF state the microcontroller forces the
transceiver to SLEEP by setting SLPTR = “1”. The transceiver awakes when the
microcontroller releases bit SLPTR.
The transceiver module differentiates between eight interrupt events. Internally all
pending interrupt are stored in a separate bit of the interrupt status register
(IRQ_STATUS). Each interrupt is enabled by setting the corresponding bit in the
interrupt mask register (IRQ_MASK). If an IRQ is enabled an interrupt service routine
must be defined to handle the IRQ. A pending IRQ is cleared automatically if an
Interrupt service routine is called. It is also possible to handle IRQs manually by polling
the IRQ_STATUS register. If an IRQ occurred, the appropriate IRQ_STATUS register
bit is set. The IRQ can be cleared by writing ‘1’ to the register bit. It is recommended to
clear the corresponding status bit before enabling an interrupt.
Interrupts are not cleared automatically when the event that caused them vanishes.
More information about interrupt handling by the controller can be found in section
"Interrupts" on page
The supported interrupts for the Basic Operating Mode are summarized in
page 35.
SLPTR Bit
“0”
“0”
“0”
“1”
"Operating Modes" on page
“1”
“1”
“1”
“0”
Table 9-1
Description
Starts frame transmission
Starts TX_ARET transaction
Takes the radio transceiver into SLEEP state
Takes the radio transceiver back into TRX_OFF state;
212.
below. The radio transceiver states are explained in detail in
36.
8266B-MCU Wireless-03/11
Table 9-2 on
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