PIC16LF1824-I/ST Microchip Technology, PIC16LF1824-I/ST Datasheet - Page 12

• Manufacturer Part Number: PIC16LF1824-I/ST
• Description: IC PIC MCU 8BIT 14KB FSH 14TSSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1824-I/ST

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP (0.173", 4.40mm Width)
• Controller Family/series: PIC16LF
• No. Of I/o's: 12
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF182X/PIC12F/LF1822
4.0
In Program/Verify mode, the program memory and the
configuration
programmed
ICSPCLK are used for the data and the clock,
respectively. All commands and data words are
transmitted LSb first. Data changes on the rising edge
of the ICSPCLK and latched on the falling edge. In
Program/Verify
ICSPCLK are Schmitt Trigger inputs. The sequence
that enters the device into Program/Verify mode
places all other logic into the Reset state. Upon
entering
automatically configured as high-impedance inputs
and the address is cleared.
4.1
There are two different methods of entering Program/
Verify mode via high-voltage:
• V
• V
4.1.1
To enter Program/Verify mode via the V
the following sequence must be followed:
1.
2.
3.
The V
code prior to entering Program/Verify mode. For
example, when Configuration Word 1 has MCLR
disabled (MCLRE = 0), the power-up time is disabled
(PWRTE = 0), the internal oscillator is selected
(F
driven by the user application, the device will execute
code. Since this may prevent entry, V
mode is strongly recommended. See the timing
diagram in Figure 8-2.
4.1.2
To enter Program/Verify mode via the V
the following sequence must be followed:
1.
2.
3.
The V
device when V
necessary to disconnect V
mode. See the timing diagram in Figure 8-1.
DS41390C-page 12
OSC
PP
DD
Hold ICSPCLK and ICSPDAT low. All other pins
should be unpowered.
Raise the voltage on MCLR from 0V to V
Raise the voltage on V
desired operating voltage.
Hold ICSPCLK and ICSPDAT low.
Raise the voltage on V
operating voltage.
Raise the voltage on MCLR from V
to V
PP
DD
= 100), and ICSPCLK and ICSPDAT pins are
– First entry mode
– First entry mode
-first entry prevents the device from executing
IHH
-first method is useful when programming the
PROGRAM/VERIFY MODE
High-Voltage Program/Verify Mode
Entry and Exit
Program/Verify
.
V
V
PP
DD
in
memory
DD
– FIRST ENTRY MODE
– FIRST ENTRY MODE
mode
serial
is already applied, for it is not
both
can
DD
DD
fashion.
mode,
from 0V to the desired
DD FROM
to enter Program/Verify
the
be
accessed
ICSPDAT
ICSPDAT
all
DD
PP
DD
PP
0V to the
-first method
-first method
or below
-first entry
Advance Information
I/Os
IHH
.
and
and
and
are
4.1.3
To exit Program/Verify mode take MCLR to V
lower (V
4.2
The Low-Voltage Programming mode allows the
PIC16F/LF182X and PIC12F/LF1822 devices to be
programmed using V
When the LVP bit of Configuration Word 2 register is
set to ‘1’, the low-voltage ICSP programming entry is
enabled. To disable the Low-Voltage ICSP mode, the
LVP bit must be programmed to ‘0’. This can only be
done while in the High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify modes
requires the following steps:
1.
2.
The key sequence is a specific 32-bit pattern, '0100
1101 0100 0011 0100 1000 0101 0000' (more
easily remembered as MCHP in ASCII). The device will
enter Program/Verify mode only if the sequence is
valid. The Least Significant bit of the Least Significant
nibble must be shifted in first.
Once the key sequence is complete, MCLR must be
held at V
maintained.
For low-voltage programming timing, see Figure 8-8
and Figure 8-9.
Exiting Program/Verify mode is done by no longer
driving MCLR to V
Note:
MCLR is brought to V
A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
IL
IL
Low-Voltage Programming (LVP)
Mode
). See Figures 8-3 and 8-4.
for as long as Program/Verify mode is to be
PROGRAM/VERIFY MODE EXIT
To enter LVP mode, the LSB of the Least
Significant nibble must be shifted in first.
This
sequence on other parts.
IL
differs
. See Figure 8-8 and Figure 8-9.
DD
 2010 Microchip Technology Inc.
IL
only, without high voltage.
from
.
entering
the
DD
key
or