XRT75R03IVTR-F Exar Corporation, XRT75R03IVTR-F Datasheet - Page 23

• Manufacturer Part Number: XRT75R03IVTR-F
• Description: IC LIU E3/DS3/STS-1 3CH 128LQFP
• Manufacturer: Exar Corporation

Specifications of XRT75R03IVTR-F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CONTROL AND ALARM INTERFACE
GENERAL CONTROL PINS
JITTER ATTENUATOR INTERFACE
xr
xr
xr
xr
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
P
P
P
44
IN
122
123
62
70
IN
IN
#
#
#
S
S
S
IGNAL
HOST/HW
IGNAL
IGNAL
JA0
RXA
RXB
ICT
N
N
N
AME
AME
AME
T
T
****
****
T
YPE
YPE
YPE
I
I
I
External Resistor of 3.01K
Should be connected between RxA and RxB for internal bias.
External Resistor of 3.01K
Should be connected between RxA and RxB for internal bias.
In-Circuit Test Input
Setting this pin "Low" causes all digital and analog outputs to go into a high-
impedance state to allow for in-circuit testing. For normal operation, set this pin
"High".
N
HOST/Hardware Mode Select:
Tie this pin “High” to configure the XRT75R03 in HOST mode. Tie this “Low” to
configure in Hardware mode.
When the XRT75R03 is configured in HOST mode, the states of many of the dis-
crete input pins are controlled by internal register bits.
N
Jitter Attenuator Select 0:
In Hardware Mode, this pin along with pin 42 configures the Jitter Attenuator as
shown in the table below.
N
OTE
OTE
OTES
: This pin is internally pulled “High".
: This pin is internally pulled up.
1. The setting of these input pins applies globally to all three (3) channels
2. This input pin is ignored and should be tied to GND if the XRT75R03 is
:
in the XRT75R03.
configured to operate in the Host Mode.
JA0
0
0
1
1
20
:
± 1%.
± 1%.
JA1
0
1
0
1
D
D
D
ESCRIPTION
ESCRIPTION
ESCRIPTION
Disable Jitter Attenuator
Disable Jitter Attenuator
16 bit FIFO Depth
32 bit FIFO Depth
Mode
XRT75R03
REV. 1.0.8