DS90UB903QSQ/NOPB National Semiconductor, DS90UB903QSQ/NOPB Datasheet
DS90UB903QSQ/NOPB
Specifications of DS90UB903QSQ/NOPB
Related parts for DS90UB903QSQ/NOPB
DS90UB903QSQ/NOPB Summary of contents
Page 1
... Features ■ 10 MHz to 43 MHz input PCLK support ■ 210 Mbps to 903 Mbps data throughput Typical Application Diagram TRI-STATE® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation DS90UB903Q/DS90UB904Q ■ Single differential pair interconnect ■ Bidirectional control interface channel with I ■ ...
Page 2
Block Diagrams www.national.com FIGURE 2. Block Diagram FIGURE 3. Application Block Diagram 2 30125428 30125429 ...
Page 3
Ordering Information NSID Package Description DS90UB903QSQE 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch DS90UB903QSQ 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch DS90UB903QSQX 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm ...
Page 4
DS90UB903Q Serializer Pin Descriptions Pin Name Pin No. I/O, Type LVCMOS PARALLEL INTERFACE DIN[20: Inputs, LVCMOS 40, 39, 38, 37, w/ pull down 36, 35, 33, 32, 30, 29, 28, 27, 26, 25, 24, 23 ...
Page 5
DS90UB904Q Pin Diagram Deserializer - DS90UB904Q — Top View 5 30125420 www.national.com ...
Page 6
DS90UB904Q Deserializer Pin Descriptions Pin Name Pin No. I/O, Type LVCMOS PARALLEL INTERFACE ROUT[20: 10, Outputs, 11, 12, 13, 14, LVCMOS 15, 16, 18, 19, 21, 22, 23, 24, 25, 26, 27, 28 PCLK 4 LVCMOS ...
Page 7
Pin Name Pin No. I/O, Type POWER AND GROUND VDDSSCG 3 Power, Digital VDDIO1/2/3 29, 20, 7 Power, Digital VDDD 17 Power, Digital VDDR 36 Power, Analog Rx Analog Power, 1.8V ±5% VDDCML 40 Power, Analog Bidirectional Channel Driver Power, ...
Page 8
... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – V (1.8V) DDn Supply Voltage – V DDIO LVCMOS Input Voltage I/O Voltage −0. (VDDIO + 0.3V) CML Driver I/O Voltage (V ...
Page 9
Symbol Parameter V High Level Output Voltage OH V Low Level Output Voltage OL I Output Short Circuit Current OS I TRI-STATE® Output Current PDB = 0V, OZ CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT Output Differential Voltage OD ...
Page 10
Symbol Parameter I Deserializer (Rx) VDDn DDR Supply Current (includes load current) I Deserializer (Rx) VDDIO DDIOR Supply Current (includes load current) I Deserializer (Rx) Supply DDRZ Current Power-down I DDIORZ Recommended Serializer Timing for PCLK Over recommended operating supply ...
Page 11
Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t CML Low-to-High LHT Transition Time t CML High-to-Low HLT Transition Time t Data Input Setup to PCLK DIS t Data Input Hold from PCLK ...
Page 12
Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Receiver Output Clock Period RCP t PCLK Duty Cycle PDC LVCMOS Low-to-High Transition t CLH Time t LVCMOS High-to-Low Transition CHL Time LVCMOS Low-to-High ...
Page 13
Bidirectional Control Bus AC Timing Specifications (SCL, SDA Compliant (Figure 4) Over recommended supply and temperature ranges unless otherwise specified. Symbol Parameter RECOMMENDED INPUT TIMING REQUIREMENTS f SCL Clock Frequency SCL t SCL Low Period LOW t SCL ...
Page 14
Bidirectional Control Bus DC Characteristics (SCL, SDA Over recommended supply and temperature ranges unless otherwise specified. Symbol Parameter V Input High Level IH V Input Low Level Voltage IL V Input Hysteresis HY I TRI-STATE Output Current PDB ...
Page 15
AC Timing Diagrams and Test Circuits FIGURE 6. Serializer CML Output Load and Transition Times FIGURE 5. “Worst Case” Test Pattern 15 30125452 30125446 30125447 www.national.com ...
Page 16
FIGURE 7. Serializer VOD DC Diagram FIGURE 8. Differential VTH/VTL Definition Diagram FIGURE 9. Serializer Input Clock Transition Times 16 30125448 30125430 30125416 30125434 ...
Page 17
FIGURE 10. Serializer Setup/Hold Times FIGURE 11. Serializer Data Lock Time FIGURE 12. Serializer Delay FIGURE 13. Deserializer Data Lock Time 17 30125449 30125432 30125450 30125413 www.national.com ...
Page 18
FIGURE 14. Deserializer LVCMOS Output Load and Transition Times www.national.com FIGURE 15. Deserializer Delay FIGURE 16. Deserializer Output Setup/Hold Times FIGURE 17. Receiver Input Jitter Tolerance 18 30125414 30125411 30125431 30125458 ...
Page 19
FIGURE 18. Typical Serializer Jitter Transfer Function Curve at 43 MHz FIGURE 19. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz FIGURE 20. Spread Spectrum Clock Output Profile 19 30125462 30125459 30125435 www.national.com ...
Page 20
TABLE 1. DS90UB903Q Control Registers Addr Name Bits Field (Hex) 7:1 DEVICE Device SER ID SEL 7:3 RESERVED 2 STANDBY 1 Reset DIGITAL 1 RESET0 0 DIGITAL RESET1 2 Reserved 7:0 RESERVED Reserved ...
Page 21
Addr Name Bits Field (Hex) B Reserved 7:0 RESERVED Reserved 7:3 RESERVED PCLK Detect 2 PCLK DETECT C Reserved 3 RESERVED Cable Link 0 LINK DETECT Detect Status D Reserved 7:0 RESERVED E Reserved 7:0 RESERVED F Reserved 7:0 RESERVED ...
Page 22
TABLE 2. DS90UB904Q Control Registers Addr Name Bits (Hex) 7:1 DEVICE Device DES ID SEL 7:3 RESERVED 2 REM_WAKEUP 1 Reset 1 DIGITALRESET0 0 DIGITALRESET1 RESERVED 7:6 RESERVED Auto Clock 5 AUTO_CLOCK OSS ...
Page 23
Addr Name Bits (Hex) RESERVED 7:6 RESERVED VDDIO VDDIO Control 5 CONTROL VDDIO Mode 4 VDDIO MODE PASS Pass-Through 3 3 THROUGH Auto ACK 2 AUTO ACK RESERVED 1 RESERVED RRFB 0 RRFB 4 ...
Page 24
Addr Name Bits (Hex) 7:1 SER DEV ID 7 SER ID 0 RESERVED 7:1 ID[0] INDEX 8 ID[0] Index 0 RESERVED 7:1 ID[1] INDEX 9 ID[1] Index 0 RESERVED 7:1 ID[2] INDEX A ID[2] Index 0 RESERVED 7:1 ID[3] INDEX ...
Page 25
Addr Name Bits (Hex) 21 Reserved 7:0 RESERVED 22 Reserved 7:0 RESERVED GPCR[7] GPCR[6] GPCR[5] General Purpose GPCR[4] 23 7:0 Control Reg GPCR[3] GPCR[2] GPCR[1] GPCR[0] 24 BIST 0 BIST_EN 25 BIST_ERR 7:0 BIST_ERR REM_WAKEUP_ 7:6 Remote Wake EN 26 ...
Page 26
Functional Description The DS90UB903Q/904Q FPD-Link III chipset is intended for video display applications. The Serializer/ Deserializer chipset operates from a 10 MHz to 43 MHz pixel clock fre- quency. The DS90UB903Q transforms a 21-bit wide parallel LVCMOS data bus along ...
Page 27
The appropriate pull-up resistor values will depend upon the total bus capacitance and operating speed. The DS90UB903Q/904Q bus data rate supports up to 100 kbps ...
Page 28
SLAVE CLOCK STRETCHING In order to communicate and synchronize with remote de- vices on the bus through the bidirectional control channel, slave clock stretching must be supported by the I controller/MCU. The chipset utilizes bus clock stretching ...
Page 29
CAMERA MODE OPERATION In Camera mode transactions originate from the Deseri- alizer from the Master controller (Figure core in the Deserializer will detect if a transaction is intended for the Serializer or a slave at the Serializer. ...
Page 30
Note: The user must verify that the timing variations between the different links are within their system and timing specifi- cations. GENERAL PURPOSE I/O (GPI/GPO) The DS90UB903Q/904Q has GPO and 4 GPI on the Serializer and Deserializer ...
Page 31
FIGURE 30. AT-SPEED BIST System Flow Diagram Step 1: Place the Deserializer in BIST Mode. Serializer and Deserializer power supply must be supplied. Enable the AT SPEED BIST mode on the Deserializer by set- ting the BISTEN pin High. The ...
Page 32
Step 3: Stop at SPEED BIST by turning off BIST mode in the Deserializer to determine Pass/Fail. To end BIST, the system must pull BISTEN pin of the Dese- rializer LOW. The BIST duration is fully defined by the BIS- ...
Page 33
For Remote Wake-up to function properly: • The chipset needs to be configured in Camera mode: Serializer MODE = 0 and Deserializer MODE = 1 • Serializer expects remote wake-up by default at power on. • Configure the control channel ...
Page 34
Applications Information AC COUPLING The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme. Exter- For high-speed FPD-Link III transmissions, the smallest avail- able package should be used for the AC coupling capacitor. This will help minimize ...
Page 35
Figure 36 shows a typical connection of the DS90UB904Q Deserializer. FIGURE 36. DS90UB904Q Typical Connection Diagram — Pin Control 35 30125456 www.national.com ...
Page 36
TRANSMISSION MEDIA The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and signal quality requirements. The Ser/Des employ internal termination pro- viding a clean signaling environment. The interconnect for FPD-Link III ...
Page 37
INTERCONNECT GUIDELINES See AN-1108 and AN-905 for full details. • Use 100Ω coupled differential pairs • Use the S/2S/3S rule in spacings – space between the pair – space between pairs – space to ...
Page 38
Physical Dimensions www.national.com inches (millimeters) unless otherwise noted DS90UB903Q Serializer NS Package Number SQA40A DS90UB904Q Deserializer NS Package Number SQA48A 38 ...
Page 39
Notes 39 www.national.com ...
Page 40
... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...