DS90UB903QSQ/NOPB National Semiconductor, DS90UB903QSQ/NOPB Datasheet - Page 6

• Manufacturer Part Number: DS90UB903QSQ/NOPB
• Description: IC SER/DESER 10-43MHZ 18B 40LLP
• Manufacturer: National Semiconductor

Specifications of DS90UB903QSQ/NOPB

• Function: Serializer
• Data Rate: 900Mbps
• Input Type: LVCMOS
• Output Type: CML
• Number Of Inputs: 1
• Number Of Outputs: 1
• Voltage - Supply: 1.71 V ~ 1.89 V, 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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LVCMOS PARALLEL INTERFACE
ROUT[20:0]
PCLK
GENERAL PURPOSE INPUT (GPI)
GPI[3:0]
BIDIRECTIONAL CONTROL BUS - I
SCL
SDA
MODE
ID[x]
CONTROL AND CONFIGURATION
PDB
LOCK
RES
BIST MODE
BISTEN
PASS
FPD-LINK III INTERFACE
RIN+
RIN-
DS90UB904Q Deserializer Pin Descriptions
Pin Name
11, 12, 13, 14,
15, 16, 18, 19,
21, 22, 23, 24,
25, 26, 27, 28
30, 31, 32, 33 Input, LVCMOS
38, 39, 43, 46
5, 6, 8, 9, 10,
Pin No.
47
48
35
34
44
37
41
42
4
2
1
Input, LVCMOS
Input, LVCMOS
Input, LVCMOS
Input/Output,
Input/Output,
Input, analog
Input/Output,
Input/Output,
w/ pull down
w/ pull down
Open Drain
Open Drain
I/O, Type
LVCMOS
LVCMOS
w/ pull up
LVCMOS
LVCOMS
Outputs,
2
Output,
Output,
Output,
C COMPATIBLE
CML
CML
-
Parallel data outputs.
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
General-purpose input pins can be used to control and respond to various
commands.
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to V
Data line for bidirectional control bus communication
SDA requires an external pull-up resistor to V
I
MODE = L, Master mode; Device generates and drives the SCL clock line, where
required such as Read. Device is connected to slave peripheral on the bus.
MODE = H, Slave mode (default); Device accepts SCL clock input and attached to
an I
but uses the clock generated by the Master for the data transfers.
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power
Down. Programmed control register data are NOT retained and reset to default
values.
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as Link Status.
Reserved.
Pin 46: This pin MUST be tied LOW.
Pin 43: Leave pin open.
Pins 38, 39: Route to test point or leave open if unused.
BIST Enable Pin.
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
Noninverting differential input, bidirectional control channel output. The
interconnect must be AC Coupled with a 100 nF capacitor.
Inverting differential input, bidirectional control channel output. The interconnect
must be AC Coupled with a 100 nF capacitor.
2
C Mode select
2
C controller master on the bus. Slave mode does not generate the SCL clock,
6
Description
DDIO
DDIO
.
.
Table 4