MC56F8256VLF Freescale Semiconductor, MC56F8256VLF Datasheet - Page 9

DSC 64K FLASH 60MHZ 48-LQFP

MC56F8256VLF

Manufacturer Part Number
MC56F8256VLF
Description
DSC 64K FLASH 60MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr

Specifications of MC56F8256VLF

Core Processor
56800E
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
4K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x12b, D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Product
DSCs
Processor Series
56800E
Core
56800E
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
39
Data Ram Size
8 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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2.5.2
2.5.3
2.5.4
Freescale Semiconductor
— Enhanced dual edge capture functionality
— The option to supply the source for each complementary PWM signal pair from any of the
Two independent 12-bit analog-to-digital converters (ADCs)
— 2  8 channel external inputs
— Built-in 1, 2, 4 programmable gain pre-amplifier
— Maximum ADC clock frequency up to 10 MHz
— Sequential, parallel, and independent scan mode
— First eight samples have offset, limit, and zero-crossing calculation supported
— ADC conversions can be synchronized by eFlexPWM and timer modules via internal crossbar
— Support for simultaneous and software triggering conversions
— Support for multi-triggering mode with a programmable number of conversions on each trigger
Inter-module crossbar switch (XBAR)
— Programmable internal module connections between and among the eFlexPWM, ADCs, quad
— User-defined input/output pins for PWM fault inputs, timer input/output, ADC triggers, and
Three analog comparators (CMPs)
— Selectable input source includes external pins, internal DACs
— Programmable output polarity
— Output can drive timer input, eFlexPWM fault input, eFlexPWM source, and external pin
— Output falling and rising edge detection able to generate interrupts
— 32-tap programmable voltage reference per comparator
following:
– Crossbar module outputs
– External ADC input, taking into account values set in ADC high and low limit registers
– Single conversion time of 8.5 ADC clock cycles (8.5 x 100 ns = 850 ns)
– Additional conversion time of six ADC clock cycles (6  100 ns = 600 ns)
module
timers, 12-bit DAC, CMPs, and package pins
comparator outputs
output as well as trigger ADCs
ADC
XBAR
CMP
MC56F825x/MC56F824x Product Brief, Rev. 2
Preliminary
Features
9

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