73M1866B-IMR/F Maxim Integrated Products, 73M1866B-IMR/F Datasheet - Page 52

• Manufacturer Part Number: 73M1866B-IMR/F
• Description: MICRODAA SGL PCM HIGHWAY 42-QFN
• Manufacturer: Maxim Integrated Products
• Series: MicroDAA™r

Specifications of 73M1866B-IMR/F

• Includes: PCM Highway
• Function: Data Access Arrangement (DAA)
• Interface: PCM, Serial, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 42-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Power (watts): -

73M1866B/73M1966B Data Sheet
8.8
52
Function
Mnemonic
ADJ
DAA
ENPCLKDT 0x05[4]
LAW
LIN
MASTER
PCLKDT
PCMEN
PCM Control Functions
Register
Location
0x22[6]
0x14[6:5]
0x23[0]
0x23[1]
0x23[6]
0x03[4]
0x23[7]
Type
W
W
W
W
W
W
W
R
Table 33: PCM Control Functions
Adjacent Time Slot Driver Control
Allows LSB of the PCM frame (DX) to be tri-stated during the second
half of the clock cycle. This feature allows adjacent time slots to be
used by different devices without risking a contention at the time slot
boundary.
0 = Drives DX during the entire bit time. (Default)
1 = Drives DX only during the first half of bit time.
DAA Transmit Gain
Used in conjunction with TXBST to manage transmit level. See
Section 8.8.1.
Enable PCLK Error Detection Interrupt
0 = Disables this function.
1 = Enables the detection of an interrupt resulting from an
incoherency in the PCLK count during the second set of eight
frames received after power up. (Default)
Law Compression Mode
Selects the PCM compression mode.
0 = Selects the A-law compression mode. (Default)
1 = Selects the μ-law compression mode.
Linear Mode Enable
0 = The compression modes of either A-law or μ-law are enabled.
(Default.) See the LAW bit.
1 = 16-bit linear mode.
Master/Slave Mode
The 73M1x66B is in Slave Mode by default. See Section 8.3 for
details of master and slave operation.
0 = Enables Slave Mode. (Default)
1 = Enables Master Mode.
PCLK Detect Error
PCLKDT is an interrupt resulting from the detection of two possible
events:
1. The number of PCLK periods per frame is not consistent among
the second set of eight frames after power up.
2. The number of PCLK periods per frame does not equate to any
of the acceptable PCLK frequencies. This is a maskable interrupt. It
is enabled by the ENPCLKDT bit. See Section 7.2.
PCM Transmit Enable
Controls DX and TSC. This bit must be set on completion of all
configuration changes to enable transmission on to the PCM
highway.
When powered up, the 73M1x66B PCM outputs are tri-stated. The
host must set PCMEN after setting the time/clock slot control bits to
avoid contention on the PCM highway.
Description
DS_1x66B_001
Rev. 1.6