ISL80101AIRAJZ Intersil, ISL80101AIRAJZ Datasheet

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ISL80101AIRAJZ

Manufacturer Part Number
ISL80101AIRAJZ
Description
IC REG LDO ADJ 1A 10DFN
Manufacturer
Intersil
Datasheet

Specifications of ISL80101AIRAJZ

Regulator Topology
Positive Adjustable
Voltage - Output
0.8 V ~ 5 V
Voltage - Input
2.2 V ~ 6 V
Voltage - Dropout (typical)
0.09V @ 1A
Number Of Regulators
1
Current - Output
1A (Max)
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
10-VFDFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Limit (min)
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL80101AIRAJZ-T
Manufacturer:
INTERSIL
Quantity:
20 000
Company:
Part Number:
ISL80101AIRAJZ-T
Quantity:
1 884
High Performance 1A Linear Regulator with
Programmable Current Limiting
ISL80101A
The ISL80101A is a low dropout voltage, single output LDO
with programmable current limiting. This LDO operates from
input voltages of 2.2V to 6V, and is capable of providing output
voltages of 0.8V to 5V. Other custom voltage options are
available upon request.
A sub-micron BiCMOS process is utilized for this product family
to deliver the best in class analog performance and overall
value. The programmable current limiting improves system
reliability of end applications. An external capacitor on the
soft-start pin provides an adjustable soft-starting ramp. The
ENABLE feature allows the part to be placed into a low
quiescent current shutdown mode.
This CMOS LDO will consume significantly lower quiescent
current as a function of load compared to bipolar LDOs, which
translates into higher efficiency and packages with smaller
footprints. Quiescent current is modestly compromised to
achieve a very fast load transient response.
Table 1 shows the differences between the ISL80101A and
others in its family:
February 24, 2011
FN7712.2
PART NUMBER
5.0V ± 5%
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
ISL80121-5
ISL80101A
ISL80101
10µF
C
IN
10k
R
1
0.01µF
R
C
SET
SS
I
LIMIT
10
9
8
7
6
1.75A
1.62A
0.75A
V
V
I
ENABLE
SS
(DEFAULT)
SET
IN
IN
ISL80101A
GND
1
5
V
V
OUT
OUT
ADJ
PG
1
2
3
4
PROGRAMMABLE I
100pF
C
PB
Yes
Yes
No
2.61k
R
0.464k
R
FIGURE 1. TYPICAL APPLICATION
3
2
I
LIMIT
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
SET
100k
=
10µF
C
3.3V
1.62
OUT
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
2.9x 2xV IN 1
--------------------------------------------------------
R
SET
(
Features
• ±2% V
• Very Low 212mV Dropout Voltage at V
• High Accuracy Current Limit Programmable up to 1.75A
• Very Fast Transient Response
• 100µV
• Power-Good Output
• Programmable Soft-Start
• Over-Temperature Protection
• Small 10 Ld DFN Package
Applications
• Telecommunications and Networking
• Medical Equipment
• Instrumentation Systems
• USB Devices
• Gaming
• Routers and Switchers
1.5
1.2
0.9
0.6
0.3
0.0
T
10
(
J
= -40°C to +125°C
All other trademarks mentioned are the property of their respective owners.
)
)
ADJ
RMS
V
|
Accuracy Guaranteed Over Line, Load and
IN
Copyright Intersil Americas Inc. 2010, 2011. All Rights Reserved
Output Noise
= 4.5V
V
IN
= 5.0V
R
SET (kΩ)
100
V
IN
= 5.5V
IN
= 4.5V
1000

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ISL80101AIRAJZ Summary of contents

Page 1

... FIGURE 1. TYPICAL APPLICATION CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 Intersil (and design trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Accuracy Guaranteed Over Line, Load and = 4 ...

Page 2

... Ordering Information PART NUMBER PART (Notes 1, 2) MARKING ISL80101AIRAJZ DZAC NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb- free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...

Page 3

Pin Configurations Pin Descriptions PIN NUMBER PIN NAME Output voltage. A minimum 10uF X5R/X7R output capacitor is required for stability. See “External Capacitor OUT Requirements” on page 8 for more details. 3 ADJ LDO output feedback input. ...

Page 4

... Thermal Information (Note 6) Thermal Resistance (Typical 3x3 DFN Package (Notes 4, 5 Maximum Junction Temperature (Plastic Package).........................+150°C Storage Temperature Range ............................................... -65°C to +150°C Pb-Free Reflow Profile................................................................see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Junction Temperature Range (T V Relative to GND ...........................................................................2. Range ...

Page 5

Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions: V Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to “Functional Description” on page 7 and Tech Brief ...

Page 6

Typical Operating Performance Unless otherwise noted 5V 3.3V OUT 150 +125°C 120 +25° -40° 0.2 0.4 0.6 LOAD CURRENT (A) FIGURE 2. DROPOUT vs LOAD 2.0 1.8 1.6 1.4 ...

Page 7

Typical Operating Performance Unless otherwise noted 5V 3.3V OUT ENABLE (5V/DIV) SS (1V/DIV) V OUT (2V/DIV) PG (2V/DIV) TIME (5ms/DIV) FIGURE 8. ENABLE START- OUT I = 10mA OUT TIME (20µs/div) ...

Page 8

V = 4.5V IN 1.2 0 5. 5.0V IN 0.3 0.0 10 100 R SET (kΩ) FIGURE 12. CURRENT LIMIT vs RSET AT DIFFERENT V Enable Operation The ENABLE turn-on threshold is ...

Page 9

Table 2 shows the recommended output voltage and ceramic C . OUT TABLE 2. RECOMMENDED C FOR DIFFERENT OUT 3 2 Ω Ω ( 5.0 2.61 0.287 ...

Page 10

Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION 2/2/11 FN7712 page 1, ...

Page 11

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. ...

Page 12

Package Outline Drawing L10.3x3 10 LEAD DUAL FLAT PACKAGE (DFN) Rev 6, 09/09 3.00 6 PIN 1 INDEX AREA (4X) 0.10 TOP VIEW PACKAGE OUTLINE (10 x 0.55) (10x 0.23) (8x 0.50) 1.60 TYPICAL RECOMMENDED LAND PATTERN 12 ISL80101A A ...

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