ISL95870AHRUZ-T Intersil, ISL95870AHRUZ-T Datasheet - Page 21

• Manufacturer Part Number: ISL95870AHRUZ-T
• Description: IC CTRLR PWM 1PHASE GPU 20UTQFN
• Manufacturer: Intersil

Specifications of ISL95870AHRUZ-T

• Applications: Controller, GPU Core Power
• Voltage - Input: 3.3 V ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 V ~ 5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 17 shows the overcurrent set circuit. The inductor
consists of inductance L and the DC resistance DCR. The
inductor DC current I
DCR, which is given by Equation 31:
The I
pin, creating a DC voltage drop across the resistor
R
The DC voltage difference between the OCSET pin and
the VO pin, which is given by Equation 33:
V
The IC monitors the voltage of the OCSET pin and the VO
pin. When the voltage of the OCSET pin is higher than
the voltage of the VO pin for more than 10µs, an OCP
fault latches the converter off.
The value of R
which is written as:
Where:
For example, if I
of R
Resistor R
network to sense the inductor current. To sense the
inductor current correctly not only in DC operation, but
also during dynamic operation, the R-C network time
constant R
constant L/DCR. The value of C
Equation 35:
For example, if L is 1.5µH, DCR is 4.5mΩ, and R
9kΩ, the choice of C
When an OCP fault is declared, the converter will be
latched off and the PGOOD pin will be asserted low. The
fault will remain latched until the EN pin has been pulled
below the falling EN threshold voltage V
has decayed below the falling POR threshold voltage
V
Overvoltage
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold V
for more than 2µs. For example, if the converter is
programmed to regulate 1.0V at the FB pin, that voltage
would have to rise above the typical V
V
V
C
R
VCC_THF
OCSET
OCSET
DCR
ROCSET
SEN
- R
- I
- DCR is the inductor DC resistance
OCSET
OCSET
overcurrent setpoint
the OCP fault detection circuit
OC
OCSET
OCSET
=
=
, which is given by Equation 32:
–
I
----------------------------------------- -
R
is the output DC load current that will activate
L
V
=
OCSET
.
=
⋅
OCSET
VO
OCSET
DCR
is equal to 20A x 4.5mΩ/8.5µA = 10.5kΩ.
I
--------------------------- -
8.5μA R
OC
current source sinks 8.5µA into the OCSET
I
(Ω) is the resistor used to program the
OCSET
=
L
V
OCSET
⋅
DCR
DCR
⋅
OC
and capacitor C
DCR
⋅
C
SEN
SEN
OCSET
–
is 20A and DCR is 4.5mΩ, the choice
V
L
is calculated with Equation 34,
ROCSET
creates a voltage drop across
= 1.5µH/(9kΩ x 4.5mΩ) = 0.037µF.
needs to match the inductor time
21
=
I
SEN
L
SEN
ISL95870, ISL95870A, ISL95870B
⋅
DCR
is then written as
form an R-C
OVRTH
–
I
OCSET
ENTHF
threshold of
OCSET
⋅
or if VCC
R
OCSET
(EQ. 31)
(EQ. 32)
(EQ. 34)
(EQ. 35)
(EQ. 33)
OVRTH
is
116% for more than 2µs in order to trip the OVP fault
latch. In numerical terms, that would be
116% x 1.0V = 1.16V. When an OVP fault is declared,
the converter will be latched off and the PGOOD pin will
be asserted low. The fault will remain latched until the EN
pin has been pulled below the falling EN threshold
voltage V
POR threshold voltage
Although the converter has latched-off in response to an
OVP fault, the LGATE gate-driver output will retain the
ability to toggle the low-side MOSFET on and off, in
response to the output voltage transversing the V
and V
on the low-side MOSFET to discharge the output voltage,
protecting the load. The LGATE gate-driver will turn-off
the low-side MOSFET once the FB pin voltage is lower
than the falling overvoltage threshold V
than 2µs. The falling overvoltage threshold V
typically 102%. That means if the FB pin voltage falls
below 102% x 1.0V = 1.02V for more than 2µs, the
LGATE gate-driver will turn off the low-side MOSFET. If
the output voltage rises again, the LGATE driver will
again turn on the low-side MOSFET when the FB pin
voltage is above the rising overvoltage threshold
V
the load when there is a consistent overvoltage
condition.
Undervoltage
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold V
more than 2µs. For example if the converter is
programmed to regulate 1.0V at the FB pin, that voltage
would have to fall below the typical V
84% for more than 2µs in order to trip the UVP fault
latch. In numerical terms, that would be
84% x 1.0V = 0.84V. When a UVP fault is declared, the
converter will be latched off and the PGOOD pin will be
asserted low. The fault will remain latched until the EN
pin has been pulled below the falling EN threshold
voltage V
POR threshold voltage V
Over-Temperature
When the temperature of the IC increases above the
rising threshold temperature T
state that suspends the PWM, forcing the LGATE and
UGATE gate-driver outputs low. The status of the PGOOD
pin does not change nor does the converter latch-off. The
PWM remains suspended until the IC temperature falls
below the hysteresis temperature T
normal PWM operation resumes. The OTP state can be
reset if the EN pin is pulled below the falling EN threshold
voltage V
POR threshold voltage
circuits remain functional while the IC is in the OTP state.
It is likely that the IC will detect an UVP fault because in
the absence of PWM, the output voltage decays below
the undervoltage threshold V
OVRTH
OVFTH
for more than 2µs. By doing so, the IC protects
ENTHF
ENTHF
ENTHF
thresholds. The LGATE gate-driver will turn-
or if VCC has decayed below the falling
or if VCC has decayed below the falling
or if VCC has decayed below the falling
V
V
VCC_THF
VCC_THF
VCC_THF
UVTH
OTRTH
. All other protection
.
.
.
OTHYS
, it will enter the OTP
UVTH
OVRTH
at which time
December 22, 2009
threshold of
OVFTH
for more
UVTH
OVRTH
FN6899.0
is
for