ISLA110P50IR72EV1Z Intersil, ISLA110P50IR72EV1Z Datasheet

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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. SPEED RESOLUTION ...

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Table of Contents Block Diagram ................................................... 1 Pin-Compatible Family....................................... 1 Key Specifications ............................................. 1 Table of Contents .............................................. 2 Pin Descriptions ................................................ 4 Absolute Maximum Ratings .............................. 5 Thermal Information ........................................ 5 Digital Specifications ........................................ 8 Timing Diagrams ............................................... 8 ...

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... These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ...

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Pin Descriptions LVDS [LVCMOS] PIN NUMBER NAME 1, 6, 12, 19, 24, 71 AVDD 2, 5, 13, 14, 16, 17, 18, 30, 31, 32, 33 VINN, VINP 15 20, 21 ...

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... Thermal Resistance (Typical QFN (Notes Operating Temperature . . . . . . . . . . . . . . . -40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . -65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = -40°C to +85°C (typical specifications at +25°C 105MHz 500MSPS, after completion of I2E calibration. IN SAMPLE ...

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Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V PARAMETER Sleep Mode Nap Mode Wakeup Time (Note 8) Sleep Mode Wakeup Time (Note 8) AC SPECIFICATIONS (Note 9) Differential ...

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Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V PARAMETER I2E Specifications Offset mismatch-induced spurious power I2E Settling Times Minimum Duration of Valid Analog Input (Note 13) Largest Interleave ...

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Digital Specifications PARAMETER SYMBOL CMOS INPUTS Input Current High (SDIO,RESETN,CSB,SCLK) Input Current Low (SDIO,RESETN,CSB,SCLK) Input Voltage High (SDIO,RESETN,CSB,SCLK) Input Voltage Low (SDIO,RESETN,CSB,SCLK) Input Current High (OUTMODE, NAPSLP, OUTFMT) (Note 14) Input Current Low (OUTMODE, NAPSLP, OUTFMT) Input Capacitance LVDS INPUTS ...

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Switching Specifications PARAMETER A/D OUTPUT Aperture Delay RMS Aperture Jitter Input Clock to Output Clock Propagation Delay Relative Input Clock to Output Clock Propagation Delay Matching (Note 16) Input Clock to Data Propagation Delay, LVDS Mode Output Clock to Data ...

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Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° -1dBFS 105MHz SFDR 70 65 ...

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Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° -1dBFS 105MHz 550 500 450 400 350 300 250M ...

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Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° -1dBFS 105MHz -1.0dBFS -10 IN SNR = ...

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Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V +25° -1dBFS 105MHz SFDR SNR ...

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... A/D characteristics are not well matched. Gain, offset and timing skew mismatches are of primary concern. The Intersil Interleave Engine (I2E) performs automatic interleave calibration for the offset, gain, and sample time skew mismatch between the core A/Ds. The I2E circuitry also adjusts in real-time for temperature and voltage variations ...

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RESETN is pulled low, and remains in that state until calibration is complete. The OR output returns to normal operation at that time important that the analog input be within the converter’s ...

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Best performance is obtained when the analog inputs are driven differentially. The common-mode output voltage, VCM, should be used to properly bias the inputs as shown in Figures 30 through 32 transformer will give the best noise and ...

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Internal aperture jitter is the uncertainty in the sampling instant shown in Figure 2. The internal aperture jitter combines with the input clock jitter in a root-sum-square fashion, since they are not statistically correlated, ...

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Data Format Output data can be presented in three formats: two’s complement, Gray code and offset binary. The data format is selected via the OUTFMT pin as shown in Table 3. TABLE 3. OUTFMT PIN SETTINGS OUTFMT PIN AVSS Float ...

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I2E Requirements and Restrictions Overview I2E is a blind and background capable algorithm, designed to transparently eliminate interleaving artifacts. This circuitry eliminates interleave artifacts due to offset, gain, and sample time mismatches between unit A/Ds, and across supply voltage and ...

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Configurability and Communication I2E can respond to status queries, be turned on and turned off, and generally configured via SPI programmable registers. Configuring of I2E is generally unnecessary unless the application cannot meet the requirements of Track Mode on or ...

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CSB SCLK SDIO R CSB SCLK SDIO DSW CSB t S SCLK SDIO R DSW CSB t S SCLK SDIO R A12 SDO 21 ISLA110P50 A12 A11 A10 A1 ...

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CSB SCLK SDIO INSTRUCTION/ADDRESS CSB SCLK SDIO INSTRUCTION/ADDRESS Serial Peripheral Interface A serial peripheral interface (SPI) bus is used to facilitate configuration of the device and to optimize performance. The SPI bus consists of chip select (CSB), serial clock (SCLK) ...

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... A common SPI map, which can accommodate 3 single-channel or multi-channel devices, is used for all 4 or more Intersil A/D products. Certain configuration commands (identified as Indexed in the SPI map) can be executed on a per-converter basis. This register determines which converter is being addressed for an Indexed command important to note that only a single converter can be addressed at a time ...

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TABLE 7. COARSE GAIN ADJUSTMENT NOMINAL COARSE GAIN ADJUST 0x22[3:0] Bit3 Bit2 Bit1 Bit0 TABLE 8. MEDIUM ...

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ADDRESS 0X50-0X55: I2E FREEZE THRESHOLDS This group of registers provides programming access to configure I2E’s dynamic freeze control. As with any interleave mismatch correction algorithm making estimates of the interleave mismatch errors using the digitized application input signal, there are ...

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Track state. The hysteresis quantity is a 24-bit value, constructed with bits 23 through 12 (MSBs) being assigned to 0, bits 11 through 4 assigned to this register’s value, and bits 3 through ...

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READ OUTPUT_MODE_B 0x74 READ CONFIG_STATUS 0x75 DESIRED VALUE FIGURE 45. SETTING OUTPUT_MODE_B REGISTER The procedure for setting output_mode_B is shown in Figure 45. Read the contents of output_mode_B and config_status ...

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SPI Memory Map ADDR PARAMETER BIT 7 (Hex) NAME (MSB) 00 port_config SDO Active 01 reserved 02 burst_end 03-07 reserved 08 chip_id 09 chip_version 10 device_index_A 11-1F reserved 20 offset_coarse 21 offset_fine 22 gain_coarse 23 gain_medium 24 gain_fine 25 modes ...

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ADDR PARAMETER BIT 7 (Hex) NAME (MSB) BIT 6 55 I2E AC RMS Hysteresis 56-5F reserved 60 Coarse Offset Init 61 Fine Offset Init 62 Medium Gain Init 63 Fine Gain Init 64 Sample Time Skew Init 65-6F reserved 70 ...

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ADDR PARAMETER BIT 7 (Hex) NAME (MSB) C0 test_io User Test Mode [1: Single 01 = Alternate 10 = Reserved 11 = Reserved C1 Reserved C2 user_patt 1_lsb B7 C3 user_patt1_msb B15 C4 user_patt 2_lsb B7 C5 user_patt2_msb ...

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Equivalent Circuits AVDD AVDD Ω 75kO AVDD Ω 75kO 280O Ω INPUT Ω 75kO FIGURE 48. TRI-LEVEL DIGITAL INPUTS OVDD 2mA OR 3mA DATA DATA OVDD DATA DATA 2mA OR 3mA FIGURE 50. LVDS OUTPUTS 0.535V 31 ISLA110P50 (Continued) AVDD ...

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... A/D Evaluation Platform Intersil offers an A/D Evaluation platform which can be used to evaluate any of Intersil’s high speed A/D products. The platform consists of a FPGA based data capture motherboard and a family of A/D daughtercards. This USB based platform allows a user to quickly evaluate the A/D’s performance at a user’s specific application frequency requirements ...

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Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. SNR and SINAD are either given in units of dB ...

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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries ...

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Package Outline Drawing L72.10x10C 72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN) Rev 0, 7/07 10.00 9. PIN 1 INDEX AREA (4X) 0.15 TOP VIEW PACKAGE OUTLINE 6.00 10.00 TYPICAL RECOMMENDED LAND PATTERN 11° ±1° ALL ...