DS92LV1212AMSA National Semiconductor, DS92LV1212AMSA Datasheet

IC, DESERIALIZER, 40MHZ, 10BIT, SSOP-28

DS92LV1212AMSA

Manufacturer Part Number
DS92LV1212AMSA
Description
IC, DESERIALIZER, 40MHZ, 10BIT, SSOP-28
Manufacturer
National Semiconductor
Datasheet

Specifications of DS92LV1212AMSA

Serdes Function
Deserializer
Data Rate
400Mbps
Ic Output Type
LVTTL
No. Of Inputs
1
No. Of Outputs
10
Supply Voltage Range
3V To 3.6V
Driver Case Style
SSOP
No. Of Pins
28
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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© 2000 National Semiconductor Corporation
DS92LV1212A
16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer
with Embedded Clock Recovery
General Description
The DS92LV1212A is an upgrade of the DS92LV1212. It
maintains all of the features of the DS92LV1212. The
DS92LV1212A is designed to be used with the DS92LV1021
Bus LVDS Serializer. The DS92LV1212A receives a Bus
LVDS serial data stream and transforms it into a 10-bit wide
parallel data bus and separate clock. The reduced cable,
PCB trace count and connector size saves cost and makes
PCB layout easier. Clock-to-data and data-to-data skews are
eliminated since one input receives both clock and data bits
serially. The powerdown pin is used to save power by reduc-
ing the supply current when the device is not in use. The
Deserializer will establish lock to a synchronization pattern
within specified lock times but it can also lock to a data
stream without SYNC patterns.
Block Diagram
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
DS101387
Features
n Clock recovery without SYNC patterns-random lock
n Guaranteed transition every data transfer cycle
n Chipset (Tx + Rx) power consumption
n Single differential pair eliminates multi-channel skew
n 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock)
n 10-bit parallel interface for 1 byte data plus 2 control bits
n Synchronization mode and LOCK indicator
n Flow-through pinout for easy PCB layout
n High impedance on receiver inputs when power is off
n Programmable edge trigger on clock
n Footprint compatible with DS92LV1210
n Small 28-lead SSOP package-MSA
40MHz
or UTOPIA I Interface
DS101387-1
<
November 2000
300mW (typ)
www.national.com
@

Related parts for DS92LV1212AMSA

DS92LV1212AMSA Summary of contents

Page 1

... SYNC patterns. Block Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2000 National Semiconductor Corporation Features n Clock recovery without SYNC patterns-random lock n Guaranteed transition every data transfer cycle ...

Page 2

Block Diagram (Continued) Functional Description The DS92LV1212 is a 10-bit Deserializer chip designed to receive data over heavily loaded differential backplanes at clock speeds from 16 MHz to 40 MHz. It may also be used to receive data over Unshielded ...

Page 3

Resynchronization (Continued) recommendation is to provide a feedback loop using the LOCK pin itself to control the sync request of the Serializer (SYNC1 or SYNC2). Dual SYNC pins are provided for mul- tiple control in a multi-drop application. Sending sync ...

Page 4

... RMT Patterns DIN0 Held Low-DIN1 Held High Creates an RMT Pattern DIN8 Held Low-DIN9 Held High Creates an RMT Pattern NSID DS92LV1021TMSA DS92LV1212AMSA www.national.com DS101387-23 DIN4 Held Low-DIN5 Held High Creates an RMT Pattern DS101387-25 Order Numbers Function Serializer Deserializer 4 DS101387-24 Package MSA28 MSA28 ...

Page 5

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage CMOS/TTL Output Voltage Bus LVDS Receiver Input Voltage Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 seconds) ...

Page 6

Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Receiver out Clock RCP Period t CMOS/TTL Low-to-High CLH Transition Time t CMOS/TTL High-to-Low CHL Transition Time t Deserializer Delay DD t ROUT (0-9) ...

Page 7

AC Timing Diagrams and Test Circuits FIGURE 1. “Worst Case” Deserializer ICC Test Pattern FIGURE 2. Deserializer CMOS/TTL Output Load and Transition Times FIGURE 3. Serializer Delay FIGURE 4. Deserializer Delay 7 DS101387-4 DS101387-6 DS101387-11 DS101387-12 www.national.com ...

Page 8

AC Timing Diagrams and Test Circuits Timing shown for RCLK_R/F = LOW Duty Cycle ( RDC FIGURE 6. Deserializer TRI-STATE Test Circuit and Timing www.national.com (Continued) FIGURE 5. Deserializer Setup and Hold Times 8 DS101387-13 DS101387-14 ...

Page 9

AC Timing Diagrams and Test Circuits FIGURE 7. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays FIGURE 8. Deserializer PLL Lock Time from SyncPAT (Continued) 9 DS101387-15 DS101387-22 www.national.com ...

Page 10

AC Timing Diagrams and Test Circuits SW - Setup and Hold Time (Internal data sampling window Serializer Output Bit Position Jitter JIT t = Receiver Sampling Margin Time RSM Application Information Using the DS92LV1021 and DS92LV1212A The Serializer ...

Page 11

Application Information the receiver end. Please note that in point-to-point configu- ration, the potential of offsetting the ground levels of the Serializer vs. the Deserializer must be considered. Also, Bus LVDS provides a +/− 1.2V common mode range at the ...

Page 12

Application Information Note: For the DS92LV1021, t FIGURE 12. Using t DJIT www.national.com (Continued) (max) = 70pS and t DJIT and t to Generate an Eye Pattern Mask and Validate SIgnal Quality RNM 12 DS101387-28 (min) = −300pS DJIT ...

Page 13

... REN I DVCC I DGND I AVCC I AGND I REFCLK I DS92LV1212AMSA - Deserializer DS101387-19 No. ± 15–19, Data Output CMOS level outputs. 24–28 2 Recovered Clock Rising/Falling strobe select. TTL level input. Selects RCLK active edge for strobing of ROUT data. High selects rising edge. Low selects falling edge. ...

Page 14

Truth Table INPUTS PWRDN REN LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream. 2) RCLK Active indicates the RCLK will ...

Page 15

... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted Note: Package Dimensions are in millimeters only. Order Number DS92LV1212AMSA NS Package Number MSA28 2. A critical component is any component of a life ...

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