DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 18

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F5011/5013
2.3
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and
16/16-bit
operations, in the form of single instruction iterative
divides. The following instructions and data sizes are
supported:
1.
2.
3.
4.
5.
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
TABLE 2-1:
DS70116H-page 18
DIVF
DIV.sd
DIV.sw or
DIV.s
DIV.ud
DIV.uw or
DIV.u
DIVF - 16/16 signed fractional divide
DIV.sd - 32/16 signed divide
DIV.ud - 32/16 unsigned divide
DIV.sw - 16/16 signed divide
DIV.uw - 16/16 unsigned divide
Instruction
Divide Support
signed
DIVIDE INSTRUCTIONS
and
Signed fractional divide: Wm/Wn → W0; Rem → W1
Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1
Signed divide: Wm/Wn → W0; Rem → W1
Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1
Unsigned divide: Wm/Wn → W0; Rem → W1
unsigned
integer
divide
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT
instruction as shown in Table 2-1 (REPEAT will execute
the target instruction {operand value+1} times). The
REPEAT loop count must be setup for 18 iterations of
the DIV/DIVF instruction. Thus, a complete divide
operation requires 19 cycles.
Function
Note:
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
© 2008 Microchip Technology Inc.