DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 74

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F5011/5013
10.1
The 32-bit timer can be placed in the Gated Time
Accumulation mode. This mode allows the internal T
to increment the respective timer when the gate input
signal (T2CK pin) is asserted high. Control bit TGATE
(T2CON<6>) must be set to enable this mode. In this
mode, Timer2 originates clock source. The TGATE
setting is ignored for Timer3. The timer must be
enabled (TON = 1) and the timer clock source set to
internal (TCS = 0).
The falling edge of the external signal terminates the
count operation but does not reset the timer. The user
must reset the timer in order to start counting from zero.
10.2
When a match occurs between the 32-bit timer
(TMR3/TMR2) and the 32-bit combined period register
(PR3/PR2), or between the 16-bit timer TMR3 and the
16-bit period register PR3, a special ADC trigger event
signal is generated by Timer3.
10.3
The input clock (F
has a prescale option of 1:1, 1:8, 1:64, and 1:256,
selected by control bits TCKPS<1:0> (T2CON<5:4>
and T3CON<5:4>). For the 32-bit timer operation, the
originating clock source is Timer2. The prescaler
operation for Timer3 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:
• a write to the TMR2/TMR3 register
• a write to the T2CON/T3CON register
• device Reset, such as POR and BOR
However, if the timer is disabled (TON = 0), then the
Timer 2 prescaler cannot be reset since the prescaler
clock is halted.
TMR2/TMR3 is not cleared when T2CON/T3CON is
written.
DS70116H-page 74
Timer Gate Operation
ADC Event Trigger
Timer Prescaler
OSC
/4 or external clock) to the timer
CY
10.4
During CPU Sleep mode, the timer will not operate
because the internal clocks are disabled.
10.5
The 32-bit timer module can generate an interrupt on
period match or on the falling edge of the external gate
signal. When the 32-bit timer count matches the
respective 32-bit period register, or the falling edge of
the external “gate” signal is detected, the T3IF bit
(IFS0<7>) is asserted and an interrupt will be
generated if enabled. In this mode, the T3IF interrupt
flag is used as the source of the interrupt. The T3IF bit
must be cleared in software.
Enabling an interrupt is accomplished via the
respective timer interrupt enable bit, T3IE (IEC0<7>).
Timer Operation During Sleep
Mode
Timer Interrupt
© 2008 Microchip Technology Inc.