PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 11

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

3.2.2
The REGOUT control code allows for data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register, out of the device,
over the PGDx pin. After the REGOUT control code is
received, the CPU is held Idle for 8 cycles. After these
8 cycles, an additional 16 cycles are required to clock the
data out (see Figure 3-3).
The REGOUT code is unique because the PGDx pin is
an input when the control code is transmitted to the
device. However, after the control code is processed,
the PGDx pin becomes an output as the VISI register is
shifted out.
FIGURE 3-3:
© 2009 Microchip Technology Inc.
PGCx
PGDx
Fetch REGOUT Control Code
Execute Previous Instruction, CPU Held in Idle
REGOUT SERIAL INSTRUCTION
EXECUTION
1
1
0
2
PGDx = Input
0
3
0
REGOUT SERIAL EXECUTION
4
P4
1
2
7
8
P5
LSb
1
1
2
2
3
3
4
Shift Out VISI Register<15:0>
4
5
PGDx = Output
PIC24FJ64GA1/GB0
...
Note 1: After the contents of VISI are shifted out,
6
10
11
2: Data changes on the falling edge and
11
12
PIC24FJ64GA1/GB0 devices maintain
PGDx as an output until the first rising
edge of the next clock is received.
latches on the rising edge of PGCx. For
all
Significant bit (LSb) is transmitted first.
12
13
13
14
data
14
15 16
MSb
transmissions,
P4A
0
No Execution Takes Place,
Fetch Next Control Code
1
PGDx = Input
0
2
DS39934B-page 11
0
3
the
0
4
Least