PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 28

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24FJ64GA1/GB0
TABLE 4-2:
DS39934B-page 28
FNOSC<2:0>
FWDTEN
FWPSA
GCP
GWRP
ICS<1:0>
IESO
IOL1WAY
JTAGEN
OSCIOFNC
Note 1:
Bit Field
Available on PIC24FJXXXGB0XX devices only.
PIC24FJ64GA1/GB0 CONFIGURATION BITS DESCRIPTION (CONTINUED)
CW2<10:8>
CW1<9,8>
CW1<13>
CW1<12>
CW2<15>
CW1<14>
Register
CW1<7>
CW1<4>
CW2<4>
CW2<5>
Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRCDIV) oscillator with postscaler
110 = Reserved
101 = Low-Power RC (LPRC) oscillator
100 = Secondary (SOSC) oscillator
011 = Primary (XTPLL, HSPLL, ECPLL) oscillator with PLL
010 = Primary (XT, HS, EC) oscillator
001 = Internal Fast RC (FRCPLL) oscillator with postscaler and PLL
000 = Fast RC (FRC) oscillator
Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled;
0 = Watchdog Timer enabled/disabled by user software (LPRC can be
Watchdog Timer Postscaler bit
1 = 1:128
0 = 1:32
General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = User program memory is code-protected
General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
ICD Emulator Pin Placement Select bits
11 = Emulator functions are shared with PGEC1/PGED1
10 = Emulator functions are shared with PGEC2/PGED2
01 = Emulator functions are shared with PGEC3/PGED3
00 = Reserved; do not use
Internal External Switchover bit
1 = Two-Speed Start-up enabled
0 = Two-Speed Start-up disabled
IOLOCK Bit One-Way Set Enable bit
0 = The IOLOCK bit can be set and cleared as needed (provided an
1 = The IOLOCK bit can only be set once (provided an unlocking sequence
JTAG Enable bit
1 = JTAG enabled
0 = JTAG disabled
OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
clearing the SWDTEN bit in the RCON register will have no effect)
disabled by clearing the SWDTEN bit in the RCON register)
unlocking sequence is executed)
is executed). Once IOLOCK is set, this prevents any possible future RP
register changes.
Description
© 2009 Microchip Technology Inc.