NCP5810DMUTXG ON Semiconductor, NCP5810DMUTXG Datasheet - Page 12

• Manufacturer Part Number: NCP5810DMUTXG
• Description: IC, DUAL DC/DC CONVERTER, µDFN-12
• Manufacturer: ON Semiconductor

Specifications of NCP5810DMUTXG

• Primary Input Voltage: 4.6V
• No. Of Outputs: 2
• Output Voltage: 4.6V
• No. Of Pins: 12
• Operating Temperature Range: -40°C To +85°C
• Switching Frequency Max: 1700kHz
• Termination Type: SMD
• Mounting Style: SMD/SMT
• Package / Case: UDFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TDK: VLF3010AT-4R7MR70 (1.0 mm)
TDK: MLP3216S2R7T (0.6 mm)
SUMIDA: CDH2D09BNP (1.0 mm)
MARUWA CXFU0208-4R7 (0.8 mm)
Schottky Diode Selection
negative output. The reverse voltage rating of the selected
diode must be equal to or greater than the difference
between the output voltage of the inverter and the input
voltage. The average current rating of the diode must be
greater than the maximum output load current. The peak
current rating must be larger than the maximum peak
inductor current. It is recommended to use a Schottky diode
with lower forward voltage to minimize the power
dissipation and therefore to maximize the efficiency of the
converter.
capacitance versus reverse voltage and leakage current
versus junction diode temperature. Both parameters are
impacting the efficiency in low load condition and
switching quiescent current.
limited to:
ON SEMICONDUCTOR: NSR0320MW2
ON SEMICONDUCTOR: RB521S30
ROHM: RSX051VA-30
PHILIPS: PMEG2005AEL
Input Capacitor Selection
supply C
the analog input supply C
Output Capacitor Selection
voltage and the loop stability. C
energy during the T
the T
typically a 4.7 mF low ESR multi-layer ceramic capacitor
type X5R is recommended. Moreover two 10 mF in parallel
can be used to improved the line transient rejection in
critical conduction mode of the inverter in this case see
recommendation in Buck-Boost Compensation paragraph.
Ceramic Capacitor Caution
capacitors.
dramatically with the increased applied DC voltage. This
F 6.3 V X5R should be used to bypass the power input
An external diode is required for the rectification of the
Also a particular care must be observed for parasitic
Some recommended Schottky diodes include but are not
To achieve high performances (signal integrity) one 4.7
The output capacitor directly affects the output ripple
A particular care must be observed to select ceramic
ON
INP
phase. In order to minimize the output ripple,
(PVIN) and one 1.0 F 6.3 V X5R to bypass
Actually
OFF
phase and sustain the load during
INA
capacitance
(AVIN).
OUTP
and C
can
OUTN
decrease
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NCP5810D
12
characteristic is DC bias effect that especially affects
capacitor in small case-size. The capacitance value can
drop below 50% to 70% or even more of the nominal value.
For the boost and buck-boost regulator stability viewpoint
the percentage drop in capacitance for the chosen input and
output operating voltage must be limit to 30% maximum
over operating temperature range. Also too low
capacitance will increase the output voltage ripple and the
noise. Below is a list of recommended capacitors include
but are not limited to, please consult the manufacturers for
more detailed information.
4.7 mF 6.3 V 0603
4.7 mF 10 V 0805
10.0 mF 6.3 V 0805
10.0 mF 10 V 0805
Layout Recommendations
careful attention to board layout and component
placement. To prevent electromagnetic interference (EMI)
problems and reduce voltage ripple of the device any high
current copper trace which see high frequency switching
should be optimized. Therefore, use short and wide traces
for power current paths and for power ground tracks.
the Schottky diode D1 / capacitor C4 and D2 (optional) / C3
are in the high frequency switching path where current flow
is discontinuous. These components (D1/C4) in one hand
and (D2/C3) in other hand should be placed as close as
possible to reduce parasitic inductance connection. Also it
is important to minimize the area of the SWP and SWN
nodes and used the ground plane under them to minimize
cross-talk to sensitive signals and IC. The exposed pad of
the package must be connected to ground plane of the board
that is important for EMI and thermal management. Also,
PGND and AGND pin connection must be connected to the
ground plane. In addition, the inductors track connection
L1, L2 and input bypass capacitor C1, C2 must be placed
shortly to the NCP5810D pins connection to reduce EMI.
Finally it is always good practice to keep the sensitive
tracks such as feedback connection (VS and FBN) away
from switching signal connections (SWP and SWN) by
laying the tracks on the other side of PCB. Figure 18 show
an example of optimized PCB layout.
TDK: C1608X5R0J475MT
TDK: CGB4B1X5R0J475M (0.5 mm)
TDK: C2012X5R1A475MT
MURATA: GRM219R61A475KE
TDK: C2012X5R0J106M (0.95 mm max)
TDK: C2012X5R1A106MT (1.25 mm)
The high speed operation of the NCP5810D demands
In this application both couples of elements formed by