CS43L43-KZZ Cirrus Logic Inc, CS43L43-KZZ Datasheet - Page 13

• Manufacturer Part Number: CS43L43-KZZ
• Description: IC,D/A CONVERTER,DUAL,16/18/20/24-BIT,TSSOP,16PIN
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L43-KZZ

• Rohs Compliant: YES

DS479PP3
3.8.3 I
To write to the device, follow the procedure below while adhering to the control port Switching Spec-
ifications in section 6.
1) Initiate a START condition to the I
of the address byte is the R/W bit.
2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP.
This byte points to the register to be written.
3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed
to by the MAP.
4) If the INCR bit (see section 3.8.2) is set to 1, repeat the previous step until all the desired registers
are written, then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I
initiate a repeated START condition and follow the procedure detailed from step 1. If no further
writes to other registers are desired, initiate a STOP condition to the bus.
3.8.4 I
To read from the device, follow the procedure below while adhering to the control port Switching
Specifications.
1) Initiate a START condition to the I
of the address byte is the R/W bit.
2) After transmitting an acknowledge (ACK), the device will then transmit the contents of the regis-
ter pointed to by the MAP. The MAP will contain the address of the last register written to the MAP,
or the default address (see section 3.9) if an I
3) Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.
Continue providing a clock and issue an ACK after each byte until all the desired registers are read,
then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I
initiate a repeated START condition and follow the procedure detailed from step 1. If no further reads
from other registers are desired, initiate a STOP condition to the bus.
2
2
C Write
C Read
S D A
S C L
N O T E : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P . If
o p e ra tio n is a re a d , th is b y te c o n ta in s th e d a ta o f th e re g is te r p o in te d to b y th e M A P .
S ta rt
0 0 1 0 0 0
0
Figure 8. Control Port Timing
2
2
R /W
C bus followed by the address byte, 00100000. The eighth bit
C bus followed by the address byte, 00100001. The eighth bit
2
C reads from other registers are desired, it is necessary to
2
A C K
C writes to other registers are desired, it is necessary to
2
C read is the first operation performed on the device.
D A T A
1 -8
N O T E
A C K
D A T A
1 -8
A C K
S to p
CS43L43
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