DS90CR216MTD National Semiconductor, DS90CR216MTD Datasheet - Page 13

• Manufacturer Part Number: DS90CR216MTD
• Description: Receiver IC
• Manufacturer: National Semiconductor

Specifications of DS90CR216MTD

• Driver Case Style: TSSOP
• No. Of Pins: 48
• Mounting Type: Surface Mount
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 3.3V
• Supply Voltage Max: 3.3V
• Leaded Process Compatible: No
• Supply Current: 55µA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TxIN
TxOUT+
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
AC Timing Diagrams
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 11) + ISI (Inter-symbol interference) (Note 12)
Cable Skew — typicaIIy 10 ps–40 ps per foot, media dependent
Note 11: Cycle-to-cycle jitter is less than 250 ps
Note 12: ISI is dependent on interconnect length; may be zero
Applications Information
The DS90CR215 and DS90CR216 are backward compatible
with the existing 5V Channel Link transmitter/receiver pair
(DS90CR213, DS90CR214). To upgrade from a 5V to a 3.3V
system the following must be addressed:
1. Change 5V power supply to 3.3V. Provide this supply to
CC
Pin Name
Pin Name
the V
CC
CC
CC
, LVDS V
I/O
I/O
O
O
O
O
O
CC
I
I
I
I
I
I
I
I
I
I
I
I
I
and PLL V
No.
No.
21
21
3
3
1
1
1
1
4
5
1
2
1
3
3
3
1
1
DS90CR215 Pin Descriptions — Channel Link Transmitter
DS90CR216 Pin Descriptions — Channel Link Receiver
TTL level input.
Positive LVDS differential data output.
Negative LVDS differential data output.
TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATEs the outputs, ensuring low current at power
down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pins for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
TTL level data outputs.
Positive LVDS differential clock input.
Negative LVDS differential clock input.
CC
(Continued)
.
FIGURE 18. Receiver LVDS Input Skew Margin
13
2. Transmitter input and control inputs except 3.3V TTL/
3. The receiver powerdown feature when enabled wilI lock
CMOS levels. They are not 5V tolerant.
receiver output to a logic low. However, the 5V/66 MHz
receiver maintain the outputs in the previous state when
powerdown occurred.
Description
Description
01290920
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