PIC18LF8490-I/PT Microchip Technology, PIC18LF8490-I/PT Datasheet
PIC18LF8490-I/PT
Specifications of PIC18LF8490-I/PT
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PIC18LF8490-I/PT Summary of contents
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... Note 1: The I C™ interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 1. Module: MSSP In its current implementation, the I the anomalies ...
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... Wait for the system to become idle before setting the RCEN bit. This requires a check for the following bits to be clear: ACKEN, RCEN, PEN, RSEN and SEN. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. ...
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... T1CKPS1:T1CKPS0 bit values. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 7. Module: CCP The CCP1 and CCP2 configured for PWM mode, with 1:1 Timer2 prescaler and duty cycle set to the ...
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... TXxIF or by writing TX9D at the beginning of the V Interrupt Service Routine, or only write to TX9D when a (TRMT = 1). Date Codes that pertain to this issue: All engineering and production devices. Units Conditions LSb and V - REF REF REF LSb and V REF SS DD transmission is not in progress © 2007 Microchip Technology Inc. ...
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... TMRxL and TMRxH. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 14. Module: Timer1/Timer3 When Timer1 or Timer3 is in External Clock Synchronized mode and the external clock period is between 1 and skipped ...
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... MOVWF BSR instead of: MOVFF TEMP, BSR another alternative, the following work around shown in Example 1 can be used. This example overwrites the Fast Return register by making a dummy call to Foo with the fast option in the high priority service routine. © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F6390/6490/8390/8490 The code segment shown in Example 2 demonstrates the work around using the C18 compiler. An optimized C18 version is also pro- vided in Example 3. This example illustrates how it reduces the instruction cycle count from C18 C Compiler, 10 cycles to 3 ...
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... SEN bit will be clear, indicating the bus is Idle. Clearing and setting the SSPEN bit will also reset 2 the I C peripheral and clear the PEN, RSEN and SEN status bits. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. to clear CY ® ICD 2 ...
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... SPI Slave mode, ensure that the SSPOV bit is clear before disabling the module. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 25. Module: MSSP (SPI Mode) When the SPI is using Timer2/2 as the clock ...
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... Yes, reload for a 1 second overflow ;restore BSR register, refer to note 1 ;restore working register, refer to note 1 ;restore STATUS register (if Timer1 overflow occurred) CY All engineering and production devices. ≥ 4 MHz, no wake-ups OSC within 15.25 μ 3.81 7.63 15.25 30.5 61 76.25 152.5 © 2007 Microchip Technology Inc. ...
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... TXREG. Do not load the TXREG when timer is about to overflow. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 28. Module: EUSART/AUSART In 9-Bit Asynchronous Full-Duplex Receive mode, the received data may be corrupted if the TX9D bit (TXSTA< ...
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... While keeping the LAT bits clear, configure SCL and SDA as inputs by setting their TRIS bits. Once this is done, use the SSPCON1 and SSPCON2 registers to configure the proper I mode as before. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc operation ...
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... When code execution begins following all Resets, disable the BOR by clearing the SBOREN bit (RCON<6>). Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 37. Module: Analog-to-Digital (A/D) Converter Module When the A/D clock source is selected ...
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... Rev E Document (2/2007) Added issue 36 (Power-up Timer). Added date code applicability note to issues 17-19 (EUSART), 20-24 (MSSP), 25 (MSSP – SPI 26 (Timer1 – Asynchronous Counter). Rev F Document (7/2007) Added issue 37 (A/D Converter Module). DS80207F-page 14 Mode) and © 2007 Microchip Technology Inc. ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...