AD7248ABRZ Analog Devices Inc, AD7248ABRZ Datasheet - Page 13

• Manufacturer Part Number: AD7248ABRZ
• Description: 12-BIT DACPORT (8+4) IC
• Manufacturer: Analog Devices Inc
• Series: DACPORT®r

Specifications of AD7248ABRZ

• Settling Time: 7µs
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 210mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

00 8CC9
02 8ED9
04 BF00D0
07 C705
0B EA00 00
0E 00 FF
In a multiple DAC system the double buffering of the AD7245A
allows the user to simultaneously update all DACs. In Figure
13, a 12-bit word is loaded to the input latches of each of the
DACs in sequence. Then, with one instruction to the appropri-
ate address, CS4 (i.e., LDAC) is brought LOW, updating all the
DACs simultaneously.
AD7245A—MC68000 INTERFACE
Interfacing between the MC68000 and the AD7245A is accom-
plished using the circuit of Figure 14. Once again the AD7245A
is used in the single buffered mode. A software routine for load-
ing data to the AD7245A is given in Table VI. In this example
the AD7245A is located at address E000, and the 12-bit word is
written to the DAC in one MOVE instruction.
Table V. Sample Program for Loading AD7245A from 8086
“YZWX” #YZWX
8086
ASSUME DS: DACLOAD, CS: DACLOAD
AD15
AD0
ALE
WR
DACLOAD SEGMENT AT 000
MOV CS,
CS
MOV DS,
CX
0MOV DI,
#D000
MOV MEM, : DAC LOADED WITH WXYZ
LATCH
16-BIT
LINEAR CIRCUITRY OMITTED FOR CLARITY
CS4
DATA BUS
ADDRESS BUS
ADDRESS
DECODE
: DEFINE DATA SEGMENT
: EQUAL TO CODE
: LOAD DI WITH D000
: CONTROL IS RETURNED TO
THE MONITOR PROGRAM
REGISTER
SEGMENT REGISTER
CS1
CS
LDAC
WR
DB11
DB0
CS
LDAC
WR
DB11
DB0
CS
LDAC
WR
DB11
DB0
AD7245A
AD7245A
AD7245A
01000
MICROPROCESSOR INTERFACE—AD7248A
Figure 15 shows the connection diagram for interfacing the
AD7248A to both the 8085A and 8088 microprocessors. This
scheme is also suited to the Z80 microprocessor, but the Z80
address/data bus does not have to be demultiplexed. Data to be
loaded to the AD7248A is right justified. The AD7248A is
memory mapped with a separate memory address for the input
latch high byte, the input latch low byte and the DAC latch.
Data is first written to the AD7248A input latch in two write
operations. Either the high byte or the low byte data can be
written first to the AD7248A input latch. A write to the AD7248A
DAC latch address transfers the input latch data to the DAC
latch and updates the output voltage. Alternatively, the LDAC
input can be asynchronous or can be common to a number
of AD7248As for simultaneous updating of a number of volt-
age channels.
Table VI. Sample Routine for Loading AD7245A from 68000
8085A/8088
MC68000
D0–D15
AD0–AD7
DTACK
MOVE.W
MOVE.W
MOVE.B
TRAP
A8–A15
R/W
AS
ALE
WR
LINEAR CIRCUITRY OMITTED FOR CLARITY
LINEAR CIRCUITRY OMITTED FOR CLARITY.
OCTAL
LATCH
#X,D0
D0,$E000
#228,D7
#14
ADDRESS BUS
ADDRESS/DATA BUS
ADDRESS
DECODE
DATA BUS
ADDRESS BUS
AD7245A/AD7248A
ADDRESS
DECODE
The desired DAC data,
The Data X is transferred
X, is loaded into Data
Register 0. X may be any
value between 0 and 4094
(decimal) or 0 and OFFF
(hexadecimal).
between D0 and the
DAC Latch.
Control is returned to
the System Monitor
Program using these two
instructions.
CSLSB
CSMSB
LDAC
WR
DB0–DB7
DB11
CS
LDAC
WR
DB0
AD7248A
AD7245A