AD7248ABRZ Analog Devices Inc, AD7248ABRZ Datasheet - Page 14

• Manufacturer Part Number: AD7248ABRZ
• Description: 12-BIT DACPORT (8+4) IC
• Manufacturer: Analog Devices Inc
• Series: DACPORT®r

Specifications of AD7248ABRZ

• Settling Time: 7µs
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 210mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7245A/AD7248A
A connection diagram for the interface between the AD7248A
and 68008 microprocessor is shown in Figure 16. Once again
the AD7248A acts as a memory mapped device and data is right
justified. In this case the AD7248A is configured in the auto-
matic transfer mode which means that the high byte of the input
latch has the same address as the DAC latch. Data is written to
the AD7248A by first writing data to the AD7248A low byte.
Writing data to the high byte of the input latch also transfers the
input latch contents to the DAC latch and updates the output.
An interface circuit for connections to the 6502 or 6809 micro-
processors is shown in Figure 17. Once again, the AD7248A is
memory mapped and data is right justified. The procedure for
writing data to the AD7248A is as outlined for the 8085A/8088.
For the 6502 microprocessor the φ2 clock is used to generate
the WR, while for the 6809 the E signal is used.
6502/6809
68008
A0–A19
DTACK
D0–D7
A0–A15
2 OR E
D0–D7
R/W
AS
R/W
LINEAR CIRCUITRY OMITTED FOR CLARITY
LINEAR CIRCUITRY OMITTED FOR CLARITY.
EN
ADDRESS BUS
ADDRESS BUS
DATA BUS
ADDRESS
DECODE
DATA BUS
ADDRESS
DECODE
CSLSB
CSMSB
LDAC
WR
DB0–DB7
CSLSB
CSMSB
LDAC
WR
DB0–DB7
AD7248A
AD7248A
Figure 18 shows a connection diagram between the AD7248A
and the 8051 microprocessor. The AD7248A is port mapped in
this interface and is configured in the automatic transfer mode.
Data to be loaded to the input latch low byte is output to Port 1.
Output Line P3.0, which is connected to CSLSB of the AD7248A,
is pulsed to load data into the low byte of the input latch. Puls-
ing the P3.1 line, after the high byte data has been set up on
Port 1, updates the output of the AD7248A. The WR input of the
AD7248A can be hardwired low in this application because
spurious address strobes on CSLSB and CSMSB do not occur.
8051
P3.0
P3.1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
ADDITIONAL PINS OMITTED FOR CLARITY.
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
CSLSB
CSMSB
LDAC
WR
AD7248A