AD7896BR Analog Devices Inc, AD7896BR Datasheet - Page 5

• Manufacturer Part Number: AD7896BR
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD7896BR

• Package/case: 8-SOIC
• Features: +2.7V To 5V, 12?Bit ADC In 8?Pin
• Interface Type: Serial
• Leaded Process Compatible: No
• Number Of Bits: 12
• Number Of Channels: 1
• Peak Reflow Compatible (260 C): No
• Rohs Status: RoHS non-compliant
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 10.8mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-AD7896CBZ - BOARD EVALUATION FOR AD7896CBZ
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin No.
1
2
3
4
5
6
7
8
REV. C
Mnemonic
V
V
AGND
SCLK
SDATA
DGND
CONVST
BUSY
IN
DD
Description
Analog Input. The analog input range is 0 V to V
Positive supply voltage, 2.7 V to 5.5 V.
Analog Ground. Ground reference for track-and-hold, comparator, and DAC.
Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7896.
A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for
10 ns after this falling edge so data can be accepted on the falling edge when a fast serial clock is used.
The serial clock input should be taken low at the end of the serial data transmission.
Serial Data Output. Serial data from the AD7896 is provided at this output. The serial data is clocked
out by the falling edge of SCLK, but the data can also be read on the falling edge of the SCLK. This is
possible because data bit N is valid for a specified time after the falling edge of the SCLK (data hold
time) and can be read before data bit N+1 becomes valid a specified time after the falling edge of SCLK
(data access time) (see Figure 4). Sixteen bits of serial data are provided with four leading zeros followed
by the 12 bits of conversion data. On the 16th falling edge of SCLK, the SDATA line is held for the data
hold time and then disabled (three-stated). Output data coding is straight binary.
Digital Ground. Ground reference for digital circuitry.
Convert Start. Edge-triggered logic input. On the falling edge of this input, the track-and-hold goes into
its hold mode and conversion is initiated. If CONVST is low at the end of conversion, the part goes into
power-down mode. In this case, the rising edge of CONVST “wakes up” the part.
The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin goes high on the
falling edge of CONVST and returns low when the conversion is complete.
PIN FUNCTION DESCRIPTIONS
AGND
SCLK
PIN CONFIGURATION
V
V
DD
IN
1
2
3
4
(Not to Scale)
TOP VIEW
AD7896
–5–
8
7
6
5
BUSY
CONVST
DGND
SDATA
DD
.
AD7896