AD7896BR Analog Devices Inc, AD7896BR Datasheet - Page 9

• Manufacturer Part Number: AD7896BR
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD7896BR

• Package/case: 8-SOIC
• Features: +2.7V To 5V, 12?Bit ADC In 8?Pin
• Interface Type: Serial
• Leaded Process Compatible: No
• Number Of Bits: 12
• Number Of Channels: 1
• Peak Reflow Compatible (260 C): No
• Rohs Status: RoHS non-compliant
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 10.8mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-AD7896CBZ - BOARD EVALUATION FOR AD7896CBZ
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Interface
The serial interface to the AD7896 consists of three wires: a
serial clock input (SCLK), the serial data output (SDATA), and
a conversion status output (BUSY). This allows for an easy-to-
use interface to most microcontrollers, DSP processors, and
shift registers.
Figure 4 shows the timing diagram for the read operation to the
AD7896. The serial clock input (SCLK) provides the clock
source for the serial interface. Serial data is clocked out from the
SDATA line on the falling edge of this clock and is valid on both
the rising and falling edges of SCLK. The advantage of having
the data valid on both the rising and falling edges of the SCLK
is to give the user greater flexibility in interfacing to the part and
so that a wider range of microprocessor and microcontroller inter-
faces can be accommodated. This also explains the two timing
figures t
fies how long after the falling edge of the SCLK that the next data
bit becomes valid, whereas the time t
falling edge of the SCLK that the current data bit is valid for. The
first leading zero is clocked out on the first rising edge of
SCLK; note that the first zero may be valid on the first falling
edge of SCLK even though the data access time is specified
at 60 ns (5 V [A, B, J versions only]) for the other bits (and the
SCLK high time will be 50 ns with a 10 MHz SCLK). The reason
that the first bit will be clocked out faster than the other bits is
due to the internal architecture of the part. Sixteen clock pulses
must be provided to the part to access the full conversion result.
The AD7896 provides four leading zeros followed by the 12-bit
conversion result starting with the MSB (DB11). The last data
bit to be clocked out on the penultimate falling clock edge is the
LSB (DB0). On the 16th falling edge of SCLK, the LSB (DB0)
will be valid for a specified time to allow the bit to be read on
the falling edge of SCLK, and then the SDATA line is disabled
(three-stated). After this last bit has been clocked out, the SCLK
input should remain low until the next serial data read opera-
tion. If there are extra clock pulses after the 16th clock, the
AD7896 will start over again with outputting data from its out-
put register, and the data bus will no longer be three-stated even
when the clock stops. Provided the serial clock has stopped
before the next falling edge of CONVST, the AD7896 will
continue to operate correctly with the output shift register being
reset on the falling edge of CONVST. However, the SCLK line
REV. C
4
and t
5
that are quoted on the diagram. The time t
DOUT (O/P)
SCLK (I/P)
THREE-STATE
5
specifies how long after the
t
2
=
t
3
1
= 40ns MIN,
4 LEADING ZEROS
Figure 4. Data Read Operation
t
2
2
t
4
= 60ns MAX,
t
3
4
speci-
3
t
4
t
–9–
5
= 10ns MIN,
4
must be low when CONVST goes low in order to reset the
output shift register correctly.
The serial clock input does not need to be continuous during
the serial read operation. The 16 bits of data (four leading zeros
and 12-bit conversion result) can be read from the AD7896 in a
number of bytes. However, the SCLK input must remain low
between the two bytes.
The maximum SCLK frequency is 10 MHz for 5 V operation
(giving a throughput of 100 kHz) and at 2.7 V the maximum
SCLK frequency is less than 10 MHz to allow for the longer
data access time, t
versions), 70 ns @ 5 V, 110 ns @ 2.7 V (S version)). Note that
at 3.0 V operation (A, B, J versions), an SCLK of 10 MHz
(throughput rate of 100 kHz) may be acceptable if the required
processor setup time is 0 ns (this may be possible with an ASIC
or FPGA). The data must be read in the next 10 ns, which is
specified as the data hold time, t
The AD7896 counts the serial clock edges to know which bit
from the output register should be placed on the SDATA out-
put. To ensure that the part does not lose synchronization, the
serial clock counter is reset on the falling edge of the CONVST
input provided the SCLK line is low. The user should ensure
that a falling edge on the CONVST input does not occur while
a serial data read operation is in progress.
MICROPROCESSOR/MICROCONTROLLER INTERFACE
The AD7896 provides a 3-wire serial interface that can be
used for connection to the serial ports of DSP processors and
microcontrollers. Figures 5 through 8 show the AD7896
interfaced to a number of different microcontrollers and DSP
processors. The AD7896 accepts an external serial clock and as
a result, in all interfaces shown here, the processor/controller is
configured as the master, providing the serial clock, with the
AD7896 configured as the slave in the system.
AD7896–8051 Interface
Figure 5 shows an interface between the AD7896 and the
8X51/L51 microcontroller. The 8X51/L51 is configured for its
Mode 0 serial interface mode. The diagram shows the simplest
form of the interface where the AD7896 is the only part connected
to the serial port of the 8X51/L51 and, therefore, no decoding
of the serial read operations is required.
DB11
5
t
6
= 50ns MAX @ 5V, A, B, VERSIONS
DB10
t
5
6
15
4
(60 ns @ 5 V, 100 ns @ 2.7 V (A, B, J
DB0
16
THREE-STATE
5
t
, after the SCLK edge.
6
AD7896