CS4207-DNZ Cirrus Logic Inc, CS4207-DNZ Datasheet - Page 41

• Manufacturer Part Number: CS4207-DNZ
• Description: IC Low Pwr,4/6 HD Aud Codec W/HP Amp
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS4207-DNZ

• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 3
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 110
• Voltage - Supply, Analog: 2.97 V ~ 5.25 V
• Voltage - Supply, Digital: 2.97 V ~ 5.25 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Package: 48WQFN
• Number Of Channels Per Chip: 16
• Adc/dac Resolution: 24 Bit
• Gain Control: Programmable
• Number Of Dacs: 3
• Number Of Dac Outputs: 2
• Operating Supply Voltage: 1.8|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1798

DS880F1
6.3.9
PS-Set is a Power State field which defines the current power setting of the referenced node. Since this
node is an Audio Function Group node, the actual power state is this setting. Setting this field to the D3
state for the Audio Function Group node will force all other nodes with power state control to the D3 state.
If the Power State field for this node is set to D0, then the individual power state for each converter will be
uniquely controlled via the corresponding node Power State field.
PS-Act is a Power State field which indicates the actual power state of the referenced node. Within the
Audio Function Group node, this field will always be equal to the PS-Set field (modulo the time required
to execute a power state transition).
PS-ClkStopOk is reported as a ‘1’b when the codec is capable of continuing proper operation in the ab-
sence of the HD Audio Bus BITCLK. This bit is reported only at the Audio Function Group level and is
reserved at the widget level. After accepting a low power state transition request (D3 state) to the Audio
Function Group Node, the codec will begin ramping down all the audio converters. During this time, the
PS-ClkStopOK bit will be set to ‘0’b to signify that the bus BITCLK can not be stopped. Once all the con-
verters have been ramped down, the codec will update the PS-Act bits to reflect the actual transition to
the D3 state and will then set the PS-ClkStopOk bit to a ‘1’b to report the ability of the Codec to operate
correctly while in the low power state with the BITCLK stopped. While in the low power D3 state, and with
the bus BITCLK stopped, the pin widgets of the codec which were enabled to support unsolicited respons-
es will continue to operate.
GPIO Data
Get Parameter Command Format:
Set Parameter Command Format:
Response Format:
Bits [31:28]
Bits [31:28]
CAd = X
CAd = X
31:8
Bits
7:4
3:0
Node ID = 01h
Node ID = 01h
Bits [27:20]
Bits [27:20]
Read/Write
Read Only
Read Only
Type
Verb ID = F15h
Verb ID = 715h
Bits [19:8]
Bits [19:8]
000000h
Default
0h
0h
Reserved
GPIO[7:4] Data: Not Supported.
GPIO[3:0] Data: For GPIO programmed as
inputs, this value is read only and is the sensed
value on the corresponding pin. For GPIO pro-
grammed as outputs, the value written is driven
onto the corresponding pin.
Note that if the corresponding bit in the GPIO
Enable Mask control is not set, pins configured
as outputs will not drive the associated bit value
(as the pin must be in a Hi-Z state), but the value
returned on a read will still reflect the value that
would be driven if the pin were to be enabled in
the GPIO Enable Mask control.
Parameter ID = 00h
Parameter ID = 0xh
Description
Bits [7:0]
Bits [7:0]
CS4207
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