CS42L51-CNZR Cirrus Logic Inc, CS42L51-CNZR Datasheet - Page 86

• Manufacturer Part Number: CS42L51-CNZR
• Description: IC LV Stereo Codec F/Digital Audio Apps
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-CNZR

• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q3956082

86
15.REVISION HISTORY
Revision
A1
A2
Initial Release
Renamed pin 14, FILT1+, to DAC_FILT+ and pin 16, FILT2+, to ADC_FILT+.
Added 1.5 µF capacitor recommendation to figure
Removed the 0.1µF capacitors from pins DAC_FILT+, ADC_FILT+ and VQ on the figures
Diagram (Software Mode)” on page 10
Added DAC Isolation specification to
Input Characteristics (Automotive - DNZ)” on page
Corrected specification table
Removed t
Added t
page
Adjusted timing specifications t
Specifications - Serial Port” on page
Added MIC Bias PSRR specification to
Adjusted specification table
Removed QSM clock ratios 128, 192, 256, 384 and HSM ratios 128, 192 from
Modified Digital Mix description in section
Corrected DAC Zero Cross timeout period in section
Adjusted BEEP off time settings in section
Modified BEEP description in section
Adjusted the minimum settings for the
page
Swapped bits PCMA_OVFL w/PCMB_OVFL and ADCA_OVFL w/ADCB_OVFL in register
(Read Only)” on page
Corrected Charge Pump Frequency setting in section
page
Added sections
on THD+N” on page
20.
72.
74.
s(SDO-SK)
d
timing specification from table in section
“Headphone THD+N versus Output Power Plots” on page 75
and t
78.
73.
h(SK-SDO)
“Power Consumption” on page
“Headphone Output Power Characteristics” on page
s(SD-SK)
timing specification to table in section
20.
“Analog Input Characteristics (Commercial - CNZ)” on page 13
“Beep (BEEP)” on page
and
“Noise Gate Boost (NG_BOOST) and Threshold (THRESH[3:0])” on
from 0 ns to 20 ns and t
“DC Electrical Characteristics” on page
“Digital Mix (DIGMIX)” on page
“Beep Off Time (OFFTIME[2:0])” on page
“Typical Connection Diagram (Hardware Mode)” on page
“Typical Connection Diagram (Software Mode)” on page
14.
Changes
“Switching Specifications - Serial Port” on page
“Zero Cross” on page
“Charge Pump Frequency (CHRG_FREQ[3:0])” on
25.
64.
h
from 50 ns to 20 ns in table in section
“Switching Specifications - Serial Port” on
53.
59.
and
Table 3 on page
24.
“ADC_FILT+ Capacitor Effects
19.
63.
“Typical Connection
“Status (Address 20h)
39.
CS42L51
and
11.
20.
“Switching
DS679F1
“Analog
10.