CS8406-DZZR Cirrus Logic Inc, CS8406-DZZR Datasheet - Page 14

• Manufacturer Part Number: CS8406-DZZR
• Description: IC,Digital Audio Transmitter,CMOS,TSSOP,28PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

14
VLRCK
TXP(N)
Note:
V/C/U
TCBL
SDIN
1. T
2. T
3. T
a) With TCBL set to input, driving TCBL high for >3 OMCK clocks will cause a frame start, as well as a new
channel status block start.
b) If the serial audio input port is in Slave Mode and TCBL is set to output, the start of the A channel sub-
frame will be aligned with the leading edge of ILRCK.
The timing of TCBL, VLRCK, C, U, and V are illustrated in
tual word clock signal, and is used here only to illustrate the timing of the C, U, and V bits. In Stereo Mode
VLRCK = AES3 frame rate and in Mono Mode VLRCK = 2 x AES3 frame rate. If the serial audio input port
is set to Slave Mode and TCBL is an output, VLRCK = ILRCK when SILRPOL = 0 and VLRCK = ILRCK
when SILRPOL = 1. If the serial audio input port is set to master mode and TCBL is an input,
VLRCK = ILRCK when SILRPOL = 0 and VLRCK = ILRCK when SILRPOL = 1.
setup
hold
th
> 3 OMCKS if TCBL is an input
Tth
= 0
Z
≥ 15% AES3 frame rate
Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data, Stereo Mode
Data [4]
Data [0]
Tsetup
VCU[0]
Y
Thold
Data [5]
Data [1]
VCU[1]
X
Data [6]
Data [2]
Figure 8
VCU[2]
Y
Data [7]
and
Data [3]
Figure
9. VLRCK is the internal vir-
VCU[3]
X
Data [8]
Data [4]
CS8406
DS580F4
VCU[4]