CS8406-DZZR Cirrus Logic Inc, CS8406-DZZR Datasheet - Page 19

• Manufacturer Part Number: CS8406-DZZR
• Description: IC,Digital Audio Transmitter,CMOS,TSSOP,28PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

DS580F4
8. CONTROL PORT REGISTER BIT DEFINITIONS
8.1
8.2
8.3
7
0
7
0
7
0
Memory Address Pointer (MAP)
Not a register
Default = ‘000000’
Control 2 (02h)
MMT - Select AES3 transmitter mono or stereo operation
Default = ‘0’
0 - Normal stereo operation
1 - Output either left or right channel inputs into consecutive subframe outputs (Mono Mode, left or right is
determined by MMTLR bit)
MAP[6:0] - Memory Address Pointer. Will automatically increment after each read or write.
VSET - Transmitted Validity bit level
Default = ‘0’
0 - Indicates data is valid, linear PCM audio data
1 - Indicates data is invalid or not linear PCM audio data
MUTEAES - Mute control for the AES transmitter output
Default = ‘0’
0 - Not Muted
1 - Muted
INT1:0 - Interrupt output pin (INT) control
Default = ‘00’
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier
Default = ‘0’
0 - TCBL is an input
1 - TCBL is an output
MAP6
VSET
6
6
6
0
Control 1 (01h)
MAP5
5
5
0
5
0
MUTEAES
MAP4
4
4
4
0
MAP3
3
3
0
3
0
MAP2
MMT
INT1
2
2
2
MMTCS
MAP1
INT0
1
1
1
CS8406
MMTLR
TCBLD
MAP0
0
0
0
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