CY7C0852V-133BBC Cypress Semiconductor Corp, CY7C0852V-133BBC Datasheet - Page 7

• Manufacturer Part Number: CY7C0852V-133BBC
• Description: IC,SYNC SRAM,128KX36,CMOS,BGA,172PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0852V-133BBC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 4M (128K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 172-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS compliant by exemption

Document #: 38-06059 Rev. *I
Master Reset
The CY7C0831V undergoes a complete reset by taking its
MRST input LOW. The MRST input can switch asynchro-
nously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox
Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. MRST must be performed on the CY7C0831V after
power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports. The highest
memory location, 1FFFF is the mailbox for the right port and
1FFFE is the mailbox for the left port. Table 2 shows that in
Table 1. Address Counter and Counter-Mask Register Control Operation (Any Port)
Table 2. Interrupt Operation Example
Set Right INT
Reset Right INT
Set Left INT
Reset Left INT
Notes:
CLK
4.
5.
6.
7.
8.
X
“X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
Counter operation and mask register operation is independent of chip enables.
CE is internal signal. CE = LOW if CE
CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
OE is “Don’t Care” for mailbox operation.
At least one of B0, B1, B2, or B3 must be LOW.
MRST
Function
H
H
H
H
H
H
H
H
H
L
L
Flag
R
L
Flag
Flag
R
CNT/MSK
Flag
X
H
H
H
H
H
L
L
L
L
R/W
CNTRST
H
X
X
L
0
L
X
H
H
H
H
H
H
H
L
L
= LOW and CE
CE
[1, 6, 7, 8]
X
X
L
L
L
ADS
X
X
H
H
X
H
L
L
L
L
1
Left Port
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the
CNTEN
A
1FFFE
1FFFF
0L–16L
H
H
H
X
X
L
L
X
L
X
X
X
Master Reset
Counter Reset
Counter Load
Counter Readback Read out counter internal value on
Counter Increment Internally increment address counter
Counter Hold
Mask Reset
Mask Load
Mask Readback
Reserved
order to set the INT
address 1FFFF will assert INT
be active for a Write to generate an interrupt. A valid Read of
the 1FFFF location by the right port will reset INT
least one byte has to be active in order for a Read to reset the
interrupt. When one port Writes to the other port’s mailbox, the
INT of the port that the mailbox belongs to is asserted LOW.
The INT is reset when the owner (port) of the mailbox Reads
the contents of the mailbox. The interrupt flag is set in
a flow-thru mode (i.e., it follows the clock edge of the writing
port). Also, the flag is reset in a flow-thru mode (i.e., it follows
the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Operation
INT
X
X
H
L
L
R/W
X
H
X
L
Reset address counter to all 0s and mask
register to all 1s.
Reset counter unmasked portion to all 0s.
Load counter with external address value
presented on address lines.
address lines.
value.
Constantly hold the address value for
multiple clock cycles.
Reset mask register to all 1s.
Load mask register with value presented
on the address lines.
Read out mask register value on address
lines.
Operation undefined
R
R
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
flag, a Write operation by the left port to
[ 4, 5]
CE
X
X
L
L
R
R
Right Port
LOW. At least one byte has to
Description
A
1FFFE
1FFFF
0R–16R
X
X
Page 7 of 32
R
HIGH. At
INT
H
X
X
L
R