CY7C0852V-133BBC Cypress Semiconductor Corp, CY7C0852V-133BBC Datasheet - Page 9

• Manufacturer Part Number: CY7C0852V-133BBC
• Description: IC,SYNC SRAM,128KX36,CMOS,BGA,172PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0852V-133BBC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 4M (128K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 172-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS compliant by exemption

Document #: 38-06059 Rev. *I
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset
and Mask Load operations, and by MRST.
Retransmit
Retransmit is a feature that allows the Read of a block of
memory more than once without the need to reload the initial
address. This eliminates the need for external logic to store
and route data. It also reduces the complexity of the system
design and saves board space. An internal “mirror register” is
used to store the initially loaded address counter value. When
the counter unmasked portion reaches its maximum value set
by the mask register, it wraps back to the initial value stored in
this “mirror register.” If the counter is continuously configured
in increment mode, it increments again to its maximum value
and wraps back to the value initially stored into the “mirror
register.” Thus, the repeated access of the same data is
allowed without the need for any external logic.
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
CY7C0851V/CY7C0852V as a 72-bit single port SRAM in
which the counter of one port counts even addresses and the
counter of the other port counts odd addresses. This even-odd
address scheme stores one half of the 72-bit data in even
memory locations, and the other half in odd memory locations.
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
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