LM3559TLX/NOPB National Semiconductor, LM3559TLX/NOPB Datasheet - Page 21

• Manufacturer Part Number: LM3559TLX/NOPB
• Description: LM3559
• Manufacturer: National Semiconductor
• Series: -r

Specifications of LM3559TLX/NOPB

• Constant Current: Yes
• Constant Voltage: -
• Topology: High Side, PWM, Step-Up (Boost)
• Number Of Outputs: 2
• Internal Driver: Yes
• Type - Primary: Flash/Torch
• Type - Secondary: White LED
• Frequency: 1.8MHz ~ 2.2MHz
• Voltage - Supply: 2.5 V ~ 5.5 V
• Voltage - Output: -
• Mounting Type: Surface Mount
• Package / Case: 16-UFBGA
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LED VOLTAGE MONITOR
The LM3559 includes a 4-bit ADC which monitors the LED
forward voltage (VLED) and stores the digitized value in bits
[3:0] of the VLED Monitor Register. The highest voltage of
VLED1 or VLED2 is automatically sensed and that becomes
the sample point for the ADC. Bit 5, the ADC shutdown bit,
enables/disables the ADC with the default state set to enable
(bit [5] = 0).
AUTOMATIC CONVERSION MODE
With the ADC enabled, a conversion is performed each time
a flash pulse is started. When a flash pulse is started bit [6] of
the VLED Monitor Register (End of Conversion bit) is auto-
matically written with a ‘0’. At the end of the conversion, bit [6]
will go high signaling that the VLED data is valid. A read back
of the VLED Monitor register will clear the EOC bit.
13
MANUAL CONVERSION MODE
The VLED Monitor can be set up for manual conversion mode
by setting bit [4] of the VLED Monitor Register to '1'. When
details the VLED Monitor Automatic Conversion.
FIGURE 12. VIN Flash Monitor Example
Figure
21
this bit is set high the EOC bit (bit [6]) goes low and a con-
version is performed. When the conversion is complete, the
EOC bit goes high again. Subsequent conversions are per-
formed in manual mode by reading back the VLED Monitor
register, which resets the EOC bit and starts another conver-
sion (see
ADC DELAY
The ADC Delay register provides for a programmable delay
from 250 µs to 8 ms, in steps of 250 µs. This delay is the delay
from when the EOC bit goes low to when the VLED Monitor
samples the LED voltage. In Automatic Mode the EOC bit
goes low when the Flash LED current hits its target. In Manual
mode the EOC bit goes low at the end of a readback of the
VLED Monitor Register (or when the manual mode bit (bit 4)
is re-written with a 1).
of the VLED Monitor for both Automatic mode and Manual
mode.
Figure
14).
Figure 13
and
Figure 14
detail the timing
30102815
www.national.com