MCP3901A0-E/SS Microchip Technology, MCP3901A0-E/SS Datasheet - Page 39

• Manufacturer Part Number: MCP3901A0-E/SS
• Description: IC ENERGY METER AFE 2CH 20-SSOP
• Manufacturer: Microchip Technology

Specifications of MCP3901A0-E/SS

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): 10mW
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Ic Function: Analog Front End Device IC
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• No. Of Channels: 2
• Input Voltage: 2.2 V to 2.6 V
• Mounting Style: SMD/SMT
• Supply Voltage Max: 5.5V
• Rohs Compliant: Yes
• Interface Type: SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The position of the DR pulses vary, with respect to this
mode, to the OSR and to the PHASE settings:
• DRMODE<1:0> = 11: Both data ready pulses
• DRMODE<1:0> = 10: Data ready pulses from
• DRMODE<1:0> = 01: Data ready pulses from
• DRMODE<1:0> = 00 (Recommended and
© 2010 Microchip Technology Inc.
from ADC Channel 0 and ADC Channel 1 are
output on the DR pin.
ADC Channel 1 are output on the DR pin. The DR
from ADC Channel 0 is not present on the pin.
ADC Channel 0 are output on the DR pin. The DR
from ADC Channel 1 is not present on the pin.
Default mode): Data ready pulses from the
lagging ADC between the two are output on the
DR pin. The lagging ADC depends on the PHASE
register and on the OSR. In this mode, the two
ADCs are linked together so their data is latched
together when the lagging ADC output is ready.
6.10.2
There will be no DR pulses if DRMODE<1:0> = 00
when either one or both of the ADCs are in Reset or
shutdown. In Mode 0,0, a DR pulse only happens when
both ADCs are ready. Any DR pulse will correspond to
one data on both ADCs. The two ADCs are linked
together and act as if there was only one channel with
the combined data of both ADCs. This mode is very
practical when both ADC channels’ data retrieval and
processing need to be synchronized, as in power
metering applications.
Figure 6-8
pin with the different DRMODE and DR_LTY
configurations, while shutdown or Resets are applied.
Note:
represents the behavior of the data ready
DR PULSES WITH SHUTDOWN OR
RESET CONDITIONS
If DRMODE<1:0> = 11, the user will still
be able to retrieve the DR pulse for the
ADC not in shutdown or Reset (i.e., only
1 ADC channel needs to be awake).
MCP3901
DS22192C-page 39