AD9862BSTRL Analog Devices Inc, AD9862BSTRL Datasheet - Page 12

• Manufacturer Part Number: AD9862BSTRL
• Description: IC FRONT-END MIXED-SGNL 128-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9862BSTRL

• Rohs Status: RoHS non-compliant
• Rf Type: LMDS, MMDS
• Features: 12-bit ADC(s), 14-bit DAC(s)
• Package / Case: 128-LQFP

AD9860/AD9862
Register Name Address
General
Rx Power Down
Rx A
Rx B
Rx Misc
Rx I/F
Rx Digital
RSV
Tx Power Down
RSV
Tx A Offset
Tx A Offset
Tx B Offset
Tx B Offset
Tx A Gain
Tx B Gain
Tx PGA Gain
Tx Misc
Tx I/F
Tx Digital
Tx Modulator
NCO Tuning
Word
NCO Tuning
Word
NCO Tuning
Word
DLL
CLKOUT
Aux ADC A2
Aux ADC A2
Aux ADC A1
Aux ADC A1
Aux ADC B2
Aux ADC B2
Aux ADC B1
Aux ADC B1
Aux ADC Control 34
Aux ADC Clock
Aux DAC A
Aux DAC B
Aux DAC C
Aux DAC
Update Aux DAC 40
DAC Control
SigDelt
SigDelt
ADC Low Power
RSV
NOTES
1
2
When writing to a register with unassigned register bit(s), a logic low must be written to the unassigned bit(s). By default, after power up or RESET, all registers
are set low, except for the bits in the shaded boxes, which are set high.
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
41
42
43
49, 50
44–62
63
2
Bit 7
SDIO BiDir
V
Byp Buffer A
Byp Buffer B
Aux ADC A2 Data [1:0]
Aux ADC A1 Data [1:0]
Aux ADC B2 Data [1:0]
Aux ADC B1 Data [1:0]
Aux SPI
Slave Enable
Reserved
DAC A Offset [1:0]
DAC B Offset [1:0]
DAC A Coarse Gain
DAC B Coarse Gain
CLKOUT2 Divide Factor
REF
(diff)
Input Control ADC Div 2
Clock
Bit 6
LSB First
V
Tx Retime
SelBnot A
Sigma-Delta Control Word [3:0]
Low Power Register for Rx Path Operation below 32 MSPS
REF
REGISTER MAP (0x00–0x3F)
Neg. Fine Tune Fine Mode
Bit 5
Soft Reset
Rx Digital
Reserved for Future Use
Alt Timing
Mode
Reserved for Future Use
Q/I Order
Inv2
Refsel B
Sigma-Delta Control Word [11:4]
Reserved for Future Use
Aux ADC A2 Data [9:2]
Aux ADC A1 Data [9:2]
Aux ADC B2 Data [9:2]
Aux ADC B1 Data [9:2]
Bit 4
Rx Channel B Rx Channel A Buffer B
Three State
TxOff Enable
DAC A Offset [9:2]
DAC B Offset [9:2]
Inv TxSync
2 Data Paths
FTW [7:0]
FTW [15:8]
FTW [23:16]
Dis2
Select B
Aux DAC A
Aux DAC B
Aux DAC C
Inv C
Chip Rev ID
–12–
DLL Multiplier
Tx PGA Gain
1
Bit 3
Rx Retime
2 Channel
Tx Digital
Twos
Complement Sample
Keep –ve
Real Mix
Start B
HS Duty Cycle Shared Ref
Bit 2
RxPGA A
RxPGA B
Twos
Complement
Keep –ve
DAC A Fine Gain
DAC B Fine Gain
Inverse
Hilbert
Neg. Coarse Tune
DLL
Power Down
Refsel A
Power Down C Power Down B Power Down A
Inv B
Update C
Tx Analog Power Down [2:0]
Bit 1
Buffer A
Inv RxSync
Hilbert
Slave Enable Tx PGA Fast
2 Edges
Inv1
Select A
Update B
Interpolation Control
Coarse Modulation
Bit 0
All Rx
Clk Duty
Mux Out
Decimate
DAC A Offset
Direction
DAC B Offset
Direction
Interleaved
DLL
FAST
Dis1
Start A
CLK/4
Update A
Inv A
Flag
ADC Data
DAC Data
and Setup
and Setup
and Setup
SPI Setup
Delta Data
Purpose
Transmit
Auxiliary
Auxiliary
Reserved
Chip ID
Receive
Rx Low
Sigma-
REV. 0
Power
Setup
Setup
Setup
Clock
Setup
NCO
Path
Path