AD9865BCP Analog Devices Inc, AD9865BCP Datasheet - Page 25

• Manufacturer Part Number: AD9865BCP
• Description: IC FRONT-END MIXED-SGNL 64-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9865BCP

• Rohs Status: RoHS non-compliant
• Rf Type: HPNA, VDSL
• Features: 10-bit ADC(s), 10-bit DAC(s)
• Package / Case: 64-VFQFN, CSP Exposed Pad

RXSYNC
To add flexibility to the full-duplex digital interface port, several
programming options are available in the SPI registers. These
options are listed in Table 14. The timing for the Tx[5:0] and/or
Rx[5:0] ports can be independently changed by selecting either
the rising or falling clock edge as the sampling/validating edge
of the clock. Inverting RXCLK (via Bit 1 or Register 0x05)
affects both the Rx and Tx interface, because they both use
RXCLK.
Table 14. SPI Registers for Full-Duplex Interface
Address (Hex)
0x05
0x0B
0x0C
0x0D
0x0E
The default Tx and Rx data input formats are twos complement,
but can be changed to straight binary. The default TXSYNC and
RXSYNC settings can be changed such that the first nibble of
the word appears while TXSYNC, RXSYNC, or both are high.
Also, the least significant nibble can be selected as the first
nibble of the word (LS nibble first). The output driver strength
can also be reduced for lower data rate applications.
RXCLK
Rx[5:0]
Rx0LSB
Figure 54. Full-Duplex Rx Port Timing
Rx1MSB
t
Dv
Bit
(2)
(1)
(0)
(2)
(4)
(3)
(2)
(1)
(0)
(5)
(4)
(3)
(2)
(1)
(0)
(7)
Rx1LSB
Description
OSCIN to RXCLK
Disable RXCLK
Rx gain on Tx port
Tx 5/5 nibble
LS nibble first
TXCLK negative edge
Twos complement
Rx port three-state
Invert RXSYNC
Rx 5/5 nibble
LS nibble first
RXCLK negative edge
Twos complement
Invert RXCLK
Invert TXSYNC
Low drive strength
t
DH
Rx2MSB
Rx3LSB
Rx3MSB
Rev. A | Page 25 of 48
For the AD9865, the most significant nibble defaults to 6 bits,
and the least significant nibble defaults to 4 bits. This can be
changed so that the least significant nibble and most significant
nibble have 5 bits each. To accomplish this, set the 5/5 nibble bit
in Register 0x0C and Register 0x0D and use data pins Tx[5:1]
and Rx[5:1].
Figure 55 shows a possible digital interface between an ASIC
and the AD9865. The AD9865 serves as the master generating
the required clocks for the ASIC. This interface requires that the
ASIC reserve 16 pins for the interface, assuming a 6-bit nibble
width and the use of the Tx port for RxPGA gain control. Note
that the ASIC pin allocation can be reduced by 3, if a 5-bit
nibble width is used and the gain (or gain strobe) of the RxPGA
is controlled via the SPI port.
RxPGA CONTROL
The AD9865 contains a digital PGA in the Rx path that is used
to extend the dynamic range. The RxPGA can be programmed
over −12 dB to +48 dB with 1 dB resolution using a 6-bit word,
and with a 0 dB setting corresponding to a 2 V p-p input signal.
The 6-bit word is fed into a LUT that is used to distribute the
desired gain over three amplification stages within the Rx path.
Upon power-up, the RxPGA gain register is set to its minimum
gain of −12 dB. The RxPGA gain mapping is shown in Figure 56.
Table 15 lists the SPI registers pertaining to the RxPGA.
DIGITAL ASIC
Rx Data[5:0]
Tx Data[5:0]
RX_SYNC
TX_SYNC
Figure 55. Example of a Full-Duplex Digital Interface
CLKIN
with Optional RxPGA Gain Control via Tx[5:0]
OPTIONAL
FROM
CRYSTAL
OR MASTER CLK
GAIN
Tx[5:0]
RXSYNC
TXSYNC
RXCLK
CLKOUT1
CLKOUT2
OSCIN
Rx[5:0]
AD9865/AD9866
10/12
10/12
6
AD9865
TO
RxPGA
TO
Tx DIGITAL
FILTER
FROM
RxADC