CYII4SC6600AB-QDC Cypress Semiconductor Corp, CYII4SC6600AB-QDC Datasheet - Page 6

• Manufacturer Part Number: CYII4SC6600AB-QDC
• Description: SENSOR IMAGE COLOR CMOS 68-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SC6600AB-QDC

• Package / Case: 68-LCC
• Pixel Size: 3.5µm x 3.5µm
• Active Pixel Array: 2210H x 3002V
• Frames Per Second: 5
• Voltage - Supply: 2.5V, 3.3V
• Operating Supply Voltage: 2.5 V to 3.3 V
• Maximum Operating Temperature: + 65 C
• Minimum Operating Temperature: - 30 C
• Image Size: 2210 H x 3002 V
• Color Sensing: Color
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Sensor Architecture and Operation
Floor Plan
Figure 4
consists of the pixel array, shift registers for the readout in x and
y direction, parallel analog output amplifiers, and column
amplifiers that correct for the fixed pattern noise caused by
threshold voltage nonuniformities. Reading out the pixel array
starts by applying a y clock pulse to select a new row, followed
by a calibration sequence to calibrate the column amplifiers (row
blanking time). Depending on external bias resistors and timing,
typically this sequence takes about seven seconds every line
(baseline). This sequence is necessary to remove the Fixed
Pattern Noise of the pixel and of the column amplifiers
themselves (by a Double Sampling technique). Pixels can also
be read out in a nondestructive manner.
Two DACs are added to make the offset level of the pixel values
adjustable and equal for the two output buses. A third DAC is
used to connect the buses to a stable voltage during the row
blanking period, or reset the buses continuously in case of a
nondestructive readout.
Document Number: 001-02366 Rev. *G
shows the architecture of the designed image sensor. It
Dig. logic
s ync_x
clk_x
P ixel (0,0)
addres s able x-s hift regis ter + s ub-s ampling
S P I
column amplifiers
dummy pixels )
IMAG E C OR E
2210 x 3002
(excl. dark +
DAC in
pixel array
DAC
Figure 4. Floor Plan
S E NS OR
Two 10-bit ADCs running at 20 Msamples/s convert the analog
pixel values. The digital outputs are multiplexed to one digital
10-bit output at 40 Msamples/s. Note that these blocks are
electrically completely isolated from the sensor part, except for
the multiplexer, for which the settings are uploaded through the
shared address and data bus.
The x and y shift registers have a programmable starting point.
The possibilities of the starting point are limited because of
limitations imposed by subsampling requirements. The start
address is uploaded through the serial to parallel interface.
Most of the signals for the image core shown in
generated on-chip by the sequencer. This sequencer also allows
running the sensor in basic modes, not fully autonomous.
analog output
(2)
IBIS4-6600 CYII4SM6600AB
Dig. logic
addres s &
data bus
Page 6 of 34
Figure 4
are
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