HSP45106JC-25 Intersil, HSP45106JC-25 Datasheet - Page 2

• Manufacturer Part Number: HSP45106JC-25
• Manufacturer: Intersil

Specifications of HSP45106JC-25

• Mounting Style: Surface Mount
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Not Compliant

Block Diagram
Pinouts
Pin Descriptions
ENPOREG
ENOFREG
ENCFREG
C(15:0)
NAME
A(2:0)
GND
V
CLK
WR
CS
CC
TYPE
I
I
I
I
I
I
I
I
MICROPROCESSOR
CONTROL SIGNALS
DACSTRB
+5 power supply pin.
Ground.
Control input bus for loading phase, frequency, and timer data into the PFCS. C0 is LSB.
Address pins for selecting destination of C(15:0) data (Table 2). A0 is the LSB
Chip select (active low). Enables data to be written into Control Registers by WR.
Write enable (active low). Data is clocked into the register selected by A(2:0) on the rising edge of WR when CS
is low.
Clock. All registers, except the Control Registers clocked with WR, are clocked (when enabled) by the rising edge
of CLK.
Phase Offset Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip,
ENPOREG enables the clocking of data into the Phase Offset Register. Allows ROM address to be updated
regardless of ENPHAC.
Offset Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENOFREG enables the clocking of data into the Offset Frequency Register.
Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENCFREG enables the clocking of data into the Center Frequency Register.
2
COS15
COS14
COS13
COS12
COS10
COS11
INTERFACE
COS9
COS8
COS7
COS6
COS5
COS4
COS3
COS2
COS1
COS0
TICO
DISCRETE
GND
OEC
V
CC
CLOCK
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
FREQUENCY
CONTROL
SECTION
PHASE/
HSP45106
(84 LD PLCC)
HSP45106
TOP VIEW
ARGUMENT
SIN/COS
32
DESCRIPTION
SECTION
COSINE
SINE/
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
PMSEL
MOD0
MOD1
MOD2
TEST
V
WR
GND
CS
ENCFREG
ENOFREG
INHOFR
ENTIREG
INITTAC
ENPOREG
INPHAC
PACI
INITPAC
BINFMT
PAR/SER
V
SINE
COSINE
CC
CC
16
16
October 16, 2008
FN2809.8