STA304 STMicroelectronics, STA304 Datasheet - Page 26

• Manufacturer Part Number: STA304
• Description: Audio DSPs Digital Audio Proc
• Manufacturer: STMicroelectronics

Specifications of STA304

• Mounting Style: SMD/SMT
• Package / Case: TQFP-44
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STA304
13.10Configuration Register B (CRB) : add. 5Ch
NOTE: Power-on default values will configure serial input interface as I2S Slave and the output interface as I2S Master.
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I2SO_M
SbLSb
D15
BIT
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
CK_Master
I2SO_LR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D14
I2SO_LR
CK_Pol
RST
D13
1
0
0
1
0
0
0
1
1
0
0
1
1
0
1
1
I2SO_BC
K_Master
I2SO_LRCK_Master I2S (Output) Master/Slave Selection. The I2S output interface can be
D12
I2SI_LRCK_Master
I2SO_BCK_Master
I2SI_BCK_Master
I2SO_LRCK_Pol
I2SO_BICK_Pol
I2SI_LRCK_Pol
I2SI_BICK_Pol
I2SO_MSbLSb
I2SI_MSbLSb
I2SO_Align_0
I2SO_Align_1
I2SO_Align_2
I2SI_Align_0
I2SI_Align_1
I2SI_Align_2
I2SO_BI
CK_Pol
NAME
D11
I2SO_Ali
D10
gn_2
I2SO_Ali
gn_1
I2S (Input) Alignement. Using these bits the word alignement can be
adjusted with respect to the LRCK edges. Please refer to the related
paragraph for more details. The default value is mode 1.
I2S (Input) BICK Polarity. This bit should be configured according to the
used serial protocol. In order to sample incoming data on the rising
edge (data changes on the falling edge) this bit should be set to 1. Set
to 0 to reverse the sampling edge.
I2S (Input) Master/Slave Selection. The I2S input interface can be
configured as both master or slave: if the master mode is selected (1)
the BICK line will be an output (64 x 48KHz fixed). Otherwise (0) slave
mode is selected and this line is an input.
I2S (Input) LRCK Polarity. Set to 0 to receive LEFT samples when
LRCK is low, 1 otherwise.
I2S (Input) Master/Slave Selection. The I2S input interface can be
configured as both master or slave: if the master mode is selected (1)
the LRCK line will be an output (48KHz fixed). Otherwise (0) slave mode
is selected and this line is an input (continuous frequency between
32KHz and 96KHz).
I2S (Input) MSb/LSb Selection. Use this bit to select how the sample word is
received by the I2S input interface: set to 0 to configure as LSb first, 1 MSb first.
I2S (Output) Alignemt. Using these bits the word alignement can be
adjusted with respect to the LRCK edges. Please refer to the related
paragraph for more details. The default value is mode 1.
I2S (Output) BICK Polarity. This bit should be configured according to
the used serial protocol. In order to sample outcoming data on the rising
edge (data changes on the falling edge) this bit should be set to 1. Set
to 0 to reverse the sampling edge.
I2S (Output) Master/Slave Selection. The I2S output interface can be
configured as both master or slave: if the master mode is selected (1)
the BICK line will be an output (64 x 48KHz fixed). Otherwise (0) slave
mode is selected and this line is an input.
I2S (Output) LRCK Polarity. Set to 0 to transmit LEFT samples when
LRCK is low, 1 otherwise.
configured as both master or slave: if the master mode is selected (1)
the LRCK line will be an output. Otherwise (0) slave mode is selected
and this line is an input. In any case the frequency is fixed at 48 kHz
I2S (Output) ) MSb/LSb Selection. Use this bit to select how the sample
word is transmitted by the I2S output interface: set to 0 to configure as
LSb first, 1 MSb first.
D9
I2SO_Ali
gn_0
D8
I2SI_MS
bLSb
D7
CK_Master
I2SI_LR
D6
DESCRIPTION
I2SI_LR
CK_Pol
D5
K_Master
I2SI_BC
D4
I2SI_BIC
K_Pol
D3
I2SI_Alig
n_2
D2
I2SI_Alig
D1
n_1
I2SI_Alig
D0
n_0