CS8900A-IQ3ZR Cirrus Logic Inc, CS8900A-IQ3ZR Datasheet - Page 101

• Manufacturer Part Number: CS8900A-IQ3ZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQ3ZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS271F5
5.6.4 Enabling CRC Generation and Pad-
ding
Whenever the host issues a Transmit Request
command, it must indicate whether or not the
Cyclic Redundancy Check (CRC) value
should be appended to the transmit frame, and
whether or not pad bits should be added (if
needed). Table 34 describes how to configure
the CS8900A for CRC generating and pad-
ding.
5.6.5 Individual Packet Transmission
Whenever the host has a packet to transmit, it
must issue a Transmit Request to the
CS8900A consisting of the following three op-
erations in the exact order shown:
1) The host must write a Transmit Command
2) The host must write the frame's length to
3) The host must read the BusST register
The information written to the TxCMD register
tells the CS8900A how to transmit the next
CS8900A
Crystal LAN™ Ethernet Controller
Inhibit
(Bit C)
CRC
0
1
0
1
to the TxCMD register (PacketPage base +
0144h). The contents of the TxCMD regis-
ter may be read back from the TxCMD reg-
ister (Register 9).
the TxLength register (PacketPage base +
0146h).
(Register 18)
Table 34. CRC and Paddling Configuration
TxPad
(Bit D)
Dis
0
0
1
1
Register 9, TxCMD
Pad to 64 bytes if necessary
(including CRC).
Send a runt frame if specified
length less than 60 bytes.
Pad to 60 bytes if necessary (with-
out CRC).
Send runt if specified length less
than 64. The CS8900A will not
transmit a frame that is less than 3
bytes.
Operation
CIRRUS LOGIC PRODUCT DATASHEET
frame. The bits that must be programmed in
the TxCMD register are described in Table 35.
For each individual packet transmission, the
host must issue a complete Transmit Request.
Furthermore, the host must write to the TxC-
MD register before each packet transmission,
even if the contents of the TxCMD register
does not change. The Transmit Request de-
scribed above may be in either Memory Space
or I/O Space.
5.6.6 Transmit in Poll Mode
In poll mode, Rdy4TxiE bit (Register B, Buf-
CFG, Bit 8) must be clear (Interrupt Disabled).
The transmit operation occurs in the following
order and is shown in Figure 30.
clear clear
clear set
set clear
set
6
Bit
C
D
8
9
set
7
Table 35. Tx Command Configuration
InhibitCRC When set, the CS8900A
Bit Name
TxPadDis
Tx Start
Onecoll
Force
Register 9, TxCMD
Start preamble after 5 bytes
have been transferred to the
CS8900A.
Start preamble after 381
bytes have been trans-
ferred to the CS8900A.
Start preamble after 1021
bytes have been trans-
ferred to the CS8900A.
Start preamble after entire
frame has been transferred
to the CS8900A.
When set, the CS8900A dis-
cards any frame data cur-
rently in the transmit buffer.
When set, the CS8900A will
not attempt to retransmit
any packet after a collision.
does not append the 32-bit
CRC value to the end of any
transmit packet.
When set, the CS8900A will
not add pad bits to short
frames.
Operation
101