CS8900A-IQ3ZR Cirrus Logic Inc, CS8900A-IQ3ZR Datasheet - Page 77

• Manufacturer Part Number: CS8900A-IQ3ZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQ3ZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS271F5
3) Once the CS8900A is ready to accept the
For a more detailed description of transmit,
see Section 5.6 on page 99.
4.10.9 Basic I/O Mode Receive
I/O Mode receive operations occur in the fol-
lowing order (In this example, interrupts are
enabled to signal the presence of a valid re-
ceive frame):
1) A frame is received by the CS8900A, trig-
2) The host reads the Interrupt Status Queue
3) The host reads the frame data by execut-
CS8900A
Crystal LAN™ Ethernet Controller
base + 000Ch). If Rdy4TxNOW is set, the
frame can be written. If clear, the host must
wait for CS8900A buffer memory to be-
come available. If Rdy4TxiE (Register B,
BufCFG, Bit 8) is set, the host will be inter-
rupted when Rdy4Tx (Register C, BufE-
vent, Bit 8) becomes set. If the TxBidErr bit
(Register 18, BusST, Bit 7) is set, the trans-
mit length is not valid.
frame, the host executes repetitive write in-
structions
ceive/Transmit Data Port (I/O base +
0000h) to transfer the entire frame from
host memory to CS8900A memory.
gering an enabled interrupt.
Port (I/O base + 0008h) and is informed of
the receive frame.
ing repetitive read instructions (REP IN)
from the Receive/Transmit Data Port (I/O
(REP
OUT)
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to
the
Re-
For a more detailed description of receive, see
Section 5.2 on page 78.
4.10.10 Accessing Internal Registers
To access any of the CS8900A's internal reg-
isters in I/O Mode, the host must first setup the
PacketPage Pointer. It does this by writing the
PacketPage address of the target register to
the PacketPage Pointer Port (I/O base +
000Ah). The contents of the target register is
then mapped into the PacketPage Data Port
(I/O base + 000Ch).
If the host needs to access a sequential block
of registers, the MSB of the PacketPage ad-
dress of the first word to be accessed should
be set to "1". The PacketPage Pointer will then
move to the next word location automatically,
eliminating the need to setup the PacketPage
Pointer between successive accesses (see
Figure 18).
4.10.11 Polling the CS8900A in I/O Mode
If interrupts are not used, the host can poll the
CS8900A to check if receive frames are pres-
ent and if memory space is available for trans-
mit.
base + 0000h) to transfer the frame from
CS8900A memory to host memory. Pre-
ceding the frame data are the contents of
the RxStatus register (PacketPage base +
0400h) and the RxLength register (Packet-
Page base + 0402h).
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