DS2152LN Maxim Integrated Products, DS2152LN Datasheet - Page 6

• Manufacturer Part Number: DS2152LN
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated Products

Specifications of DS2152LN

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current (max): 75 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1 DETAILED DESCRIPTION
The DS2152 T1 enhanced single-chip transceiver (SCT) contains all the necessary functions for
connection to T1 lines, whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry
automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both
DSX-1 line build-outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The on-board jitter
attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data
paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It
is also used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set
of internal registers that the user can access and control the operation of the unit. Quick access via the
parallel control port allows a single controller to handle many T1 lines. The device fully meets all the
latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12-90),
AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.
1.1 Introduction
The DS2152 is a superset version of the popular DS2151 T1 single-chip transceiver offering the new
features listed below. All of the original features of the DS2151 have been retained and software created
for the original devices is transferable into the DS2152.
1.1.1 New Features
Option for non-multiplexed bus operation
Crystal-less jitter attenuation
Additional hardware signaling capability including:
– Receive signaling reinsertion to a backplane multiframe sync
– Availability of signaling in a separate PCM data stream
– Signaling freezing
– Interrupt generated on change of signaling data
Per-channel code insertion in both transmit and receive paths
Full HDLC controller for the FDL with 16-byte buffers in both transmit and receive paths
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state
8.192MHz clock synthesizer
Per-channel loopback
Addition of hardware pins to indicate carrier loss and signaling freeze
Line interface function can be completely decoupled from the framer/formatter to allow:
– Interface to optical, HDSL, and other NRZ interfaces
– Ability to “tap” the transmit and receive bipolar data streams for monitoring purposes
– Ability to corrupt data and insert framing errors, CRC errors, etc.
Transmit and receive elastic stores now have independent backplane clocks
Ability to monitor one DS0 channel in both the transmit and receive paths
Access to the data streams in between the framer/formatter and the elastic stores
AIS generation in the line interface that is independent of loopbacks
Ability to calculate and check CRC6 according to the Japanese standard
Ability to pass the F-bit position through the elastic stores in the 2.048MHz backplane mode
Programmable in-band loop code generator and detector
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