MT90863AG Zarlink, MT90863AG Datasheet - Page 15

• Manufacturer Part Number: MT90863AG
• Description: RATE CONVERSION DIGITAL SWITCH
• Manufacturer: Zarlink

The falling edge of the frame measurement signal (FEi) is evaluated against the falling edge of the frame pulse
(F0i). Table 8 and Figure 8 describe the frame alignment register.
3.6
The MT90863 has two connection memories: the backplane connection memory and the local connection memory.
The local connection memory is partitioned into high and low parts. The IMS register provides users with the
capability of initializing the local connection memory low and the backplane connection memory in two frames. Bit
11 to bit 13 of every backplane connection memory location will be programmed with the pattern stored in bit 7 to bit
9 of the IMS register. Bit 12 to 15 of every local connection memory low location will be programmed with the
pattern stored in bits 3 to 6 of the IMS register.
The block programming mode is enabled by setting the memory block program (MBP) bit of the control register
high. When the block programming enable (BPE) bit of the IMS register is set to high, the block programming data
will be loaded into bits 11 to 13 of every backplane connection memory and bits 12 to 15 of every local connection
memory low. The other connection memory bits are loaded with zeros. When the memory block programming is
complete, the device resets the BPE bit to zero. See Figure 7 for the connection memory contents when the device
is in block programming mode.
4.0
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform time-slot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data applications, select constant throughput delay to maintain
the frame integrity of the information through the switch.
The delay through the device varies according to the type of throughput delay selected in the LV/C and BV/C bits of
the local and backplane connection memory as described in Table 16 and Table 19.
DMS Register Bits
LMS1
0
0
1
Memory Block Programming
Delay through the MT90863
LMS0
0
1
0
2 Mb/s Mode
8 Mb/s Mode
Sub-Rate
Switching
Modes
Mode
Table 3 - Mode Selection for Local Interface
Local Interface
STo13 - 15
STi13 - 15
STo0 - 15
STo0 - 11
STo4 - 15
STi0 - 15
STi0 - 11
STi4 - 15
Zarlink Semiconductor Inc.
STo0 - 3
STi0 - 3
STo12
STi12
MT90863
15
2.048 Mb/s
2.048 Mb/s
2.048 Mb/s
Sub-rate Switching Input Stream at 2.048 Mb/s
Not available
2.048 Mb/s
Sub-rate Switching Output Stream at
2.048 Mb/s
Not available
8.192 Mb/s
Not available
8.192 Mb/s
Not available
Data Rate
Data Sheet