MT90863AG Zarlink, MT90863AG Datasheet - Page 23

• Manufacturer Part Number: MT90863AG
• Description: RATE CONVERSION DIGITAL SWITCH
• Manufacturer: Zarlink

15-11
8-0
Bit
10
9
FE4
15
Read/Write Address:
Reset Value:
FE3
14
FD8-0
Name
FE4-0
CFE
FD9
FE2
13
FE1
12
Frame Evaluation Input Select. The binary value expressed in these bits refers
to the frame evaluation inputs, FEi0 to FEi23.
Complete Frame Evaluation. When CFE = 1, the frame evaluation is completed
and bits FD9 to FD0 bits contains a valid frame alignment offset. This bit is reset to
zero, when SFE bit in the IMS register is changed from 1 to 0. This bit is read-only.
Frame Delay Bit 11. The falling edge of FE is sampled during the CLK-high phase
(FD9 = 1) or during the CLK-low phase (FD9 = 0). This bit allows the
measurement resolution to 1/2 CLK cycle. This bit is read-only.
Frame Delay Bits. The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of the
IMS register changes from 1 to 0. (FD8 = MSB, FD0 = LSB). These bits are also
read-only
Table 9 - Frame Alignment (FAR) Register Bit
FE0
11
03
0000
H
CFE
10
,
H
.
FD9
Zarlink Semiconductor Inc.
9
MT90863
FD8
8
23
FD7
7
FD6
Description
6
FD5
5
FD4
4
FD3
3
FD2
2
FD1
1
Data Sheet
FD0
0